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9beaf661d6
If the CPU to affine the portal interrupt is offline at boot time affine the portal interrupt to another online CPU. If the CPU is later brought online the hotplug handler will correctly adjust the affinity. Moved common code in a function. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
134 lines
4 KiB
C
134 lines
4 KiB
C
/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DPAA_SYS_H
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#define __DPAA_SYS_H
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#include <linux/cpu.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/kthread.h>
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#include <linux/sched/signal.h>
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#include <linux/vmalloc.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_reserved_mem.h>
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#include <linux/prefetch.h>
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#include <linux/genalloc.h>
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#include <asm/cacheflush.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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/* For 2-element tables related to cache-inhibited and cache-enabled mappings */
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#define DPAA_PORTAL_CE 0
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#define DPAA_PORTAL_CI 1
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static inline void dpaa_flush(void *p)
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{
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/*
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* Only PPC needs to flush the cache currently - on ARM the mapping
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* is non cacheable
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*/
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#ifdef CONFIG_PPC
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flush_dcache_range((unsigned long)p, (unsigned long)p+64);
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#endif
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}
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#define dpaa_invalidate(p) dpaa_flush(p)
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#define dpaa_zero(p) memset(p, 0, 64)
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static inline void dpaa_touch_ro(void *p)
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{
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#if (L1_CACHE_BYTES == 32)
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prefetch(p+32);
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#endif
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prefetch(p);
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}
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/* Commonly used combo */
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static inline void dpaa_invalidate_touch_ro(void *p)
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{
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dpaa_invalidate(p);
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dpaa_touch_ro(p);
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}
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#ifdef CONFIG_FSL_DPAA_CHECKING
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#define DPAA_ASSERT(x) WARN_ON(!(x))
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#else
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#define DPAA_ASSERT(x)
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#endif
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/* cyclic helper for rings */
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static inline u8 dpaa_cyc_diff(u8 ringsize, u8 first, u8 last)
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{
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/* 'first' is included, 'last' is excluded */
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if (first <= last)
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return last - first;
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return ringsize + last - first;
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}
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/* Offset applied to genalloc pools due to zero being an error return */
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#define DPAA_GENALLOC_OFF 0x80000000
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/* Initialize the devices private memory region */
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int qbman_init_private_mem(struct device *dev, int idx, dma_addr_t *addr,
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size_t *size);
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/* memremap() attributes for different platforms */
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#ifdef CONFIG_PPC
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#define QBMAN_MEMREMAP_ATTR MEMREMAP_WB
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#else
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#define QBMAN_MEMREMAP_ATTR MEMREMAP_WC
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#endif
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static inline int dpaa_set_portal_irq_affinity(struct device *dev,
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int irq, int cpu)
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{
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int ret = 0;
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if (!irq_can_set_affinity(irq)) {
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dev_err(dev, "unable to set IRQ affinity\n");
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return -EINVAL;
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}
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if (cpu == -1 || !cpu_online(cpu))
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cpu = cpumask_any(cpu_online_mask);
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ret = irq_set_affinity(irq, cpumask_of(cpu));
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if (ret)
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dev_err(dev, "irq_set_affinity() on CPU %d failed\n", cpu);
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return ret;
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}
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#endif /* __DPAA_SYS_H */
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