Huacai Chen 9d9f5b4376 LoongArch: Make WriteCombine configurable for ioremap() ... commit 16c52e5030 upstream. LoongArch maintains cache coherency in hardware, but when paired with LS7A chipsets the WUC attribute (Weak-ordered UnCached, which is similar to WriteCombine) is out of the scope of cache coherency machanism for PCIe devices (this is a PCIe protocol violation, which may be fixed in newer chipsets). This means WUC can only used for write-only memory regions now, so this option is disabled by default, making WUC silently fallback to SUC for ioremap(). You can enable this option if the kernel is ensured to run on hardware without this bug. Kernel parameter writecombine=on/off can be used to override the Kconfig option. Cc: stable@vger.kernel.org Suggested-by: WANG Xuerui <kernel@xen0n.name> Reviewed-by: WANG Xuerui <kernel@xen0n.name> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2023-04-26 14:30:07 +02:00
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asm	LoongArch: Make WriteCombine configurable for ioremap()	2023-04-26 14:30:07 +02:00
uapi/asm	LoongArch: Add BPF JIT support	2022-10-12 16:36:20 +08:00