Junhao He 0662deae8b drivers/perf: hisi: Enable HiSilicon Erratum 162700402 quirk for HIP09 ... [ Upstream commit e10b6976f6 ] HiSilicon UC PMU v2 suffers the erratum 162700402 that the PMU counter cannot be set due to the lack of clock under power saving mode. This will lead to error or inaccurate counts. The clock can be enabled by the PMU global enabling control. This patch tries to fix this by set the UC PMU enable before set event period to turn on the clock, and then restore the UC PMU configuration. The counter register can hold its value without a clock. Signed-off-by: Junhao He <hejunhao3@huawei.com> Reviewed-by: Yicong Yang <yangyicong@hisilicon.com> Link: https://lore.kernel.org/r/20240227125231.53127-1-hejunhao3@huawei.com Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>		2024-04-13 13:07:36 +02:00
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amlogic	…
arm_cspmu	perf: arm_cspmu: Reject events meant for other PMUs	2023-11-28 17:19:54 +00:00
hisilicon	drivers/perf: hisi: Enable HiSilicon Erratum 162700402 quirk for HIP09	2024-04-13 13:07:36 +02:00
Kconfig	…
Makefile	…
alibaba_uncore_drw_pmu.c	…
apple_m1_cpu_pmu.c	…
arm-cci.c	…
arm-ccn.c	…
arm-cmn.c	perf/arm-cmn: Workaround AmpereOneX errata AC04_MESH_1 (incorrect child count)	2024-03-26 18:19:10 -04:00
arm_dmc620_pmu.c	…
arm_dsu_pmu.c	…
arm_pmu.c	…
arm_pmu_acpi.c	…
arm_pmu_platform.c	…
arm_pmuv3.c	drivers/perf: pmuv3: don't expose SW_INCR event in sysfs	2024-02-05 20:14:14 +00:00
arm_smmuv3_pmu.c	…
arm_spe_pmu.c	…
cxl_pmu.c	perf: CXL: fix CPMU filter value mask length	2024-03-26 18:19:12 -04:00
fsl_imx8_ddr_perf.c	…
fsl_imx9_ddr_perf.c	…
marvell_cn10k_ddr_pmu.c	…
marvell_cn10k_tad_pmu.c	…
qcom_l2_pmu.c	…
qcom_l3_pmu.c	…
riscv_pmu.c	drivers/perf: riscv: Disable PERF_SAMPLE_BRANCH_* while not supported	2024-04-10 16:35:58 +02:00
riscv_pmu_legacy.c	drivers: perf: ctr_get_width function for legacy is not defined	2024-03-06 14:48:38 +00:00
riscv_pmu_sbi.c	perf: RISCV: Fix panic on pmu overflow handler	2024-03-26 18:19:14 -04:00
thunderx2_pmu.c	…
xgene_pmu.c	…