Adam Ford 9d3f959b42 pmdomain: imx8mp-blk-ctrl: imx8mp_blk: Add fdcc clock to hdmimix domain ... [ Upstream commit 697624ee8a ] According to i.MX8MP RM and HDMI ADD, the fdcc clock is part of hdmi rx verification IP that should not enable for HDMI TX. But actually if the clock is disabled before HDMI/LCDIF probe, LCDIF will not get pixel clock from HDMI PHY and print the error logs: [CRTC:39:crtc-2] vblank wait timed out WARNING: CPU: 2 PID: 9 at drivers/gpu/drm/drm_atomic_helper.c:1634 drm_atomic_helper_wait_for_vblanks.part.0+0x23c/0x260 Add fdcc clock to LCDIF and HDMI TX power domains to fix the issue. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> Link: https://lore.kernel.org/r/20240203165307.7806-5-aford173@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>		2024-04-13 13:07:30 +02:00
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amlogic	pmdomain: amlogic: Fix mask for the second NNA mem PD domain	2023-11-28 17:20:00 +00:00
apple	…
bcm	pmdomain: bcm: bcm2835-power: check if the ASB register is equal to enable	2023-11-28 17:19:59 +00:00
imx	pmdomain: imx8mp-blk-ctrl: imx8mp_blk: Add fdcc clock to hdmimix domain	2024-04-13 13:07:30 +02:00
mediatek	pmdomain: mediatek: fix race conditions with genpd	2024-02-23 09:25:07 +01:00
qcom	pmdomain: qcom: rpmhpd: Drop SA8540P gfx.lvl	2024-03-26 18:19:23 -04:00
renesas	pmdomain: renesas: r8a77980-sysc: CR7 must be always on	2024-02-23 09:25:15 +01:00
rockchip	…
samsung	…
st	…
starfive	…
sunxi	…
tegra	…
ti	pmdomain: ti: Add a null pointer check to the omap_prm_domain_init	2024-04-13 13:07:30 +02:00
xilinx	…
Makefile	…