87 lines
2.2 KiB
YAML
87 lines
2.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/fpga/xlnx,fpga-selectmap.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx SelectMAP FPGA interface
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maintainers:
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- Charles Perry <charles.perry@savoirfairelinux.com>
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description: |
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Xilinx 7 Series FPGAs support a method of loading the bitstream over a
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parallel port named the SelectMAP interface in the documentation. Only
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the x8 mode is supported where data is loaded at one byte per rising edge of
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the clock, with the MSB of each byte presented to the D0 pin.
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Datasheets:
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https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
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allOf:
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- $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
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properties:
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compatible:
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enum:
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- xlnx,fpga-xc7s-selectmap
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- xlnx,fpga-xc7a-selectmap
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- xlnx,fpga-xc7k-selectmap
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- xlnx,fpga-xc7v-selectmap
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reg:
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description:
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At least 1 byte of memory mapped IO
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maxItems: 1
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prog-gpios:
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description:
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config pin (referred to as PROGRAM_B in the manual)
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maxItems: 1
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done-gpios:
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description:
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config status pin (referred to as DONE in the manual)
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maxItems: 1
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init-gpios:
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description:
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initialization status and configuration error pin
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(referred to as INIT_B in the manual)
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maxItems: 1
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csi-gpios:
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description:
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chip select pin (referred to as CSI_B in the manual)
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Optional gpio for if the bus controller does not provide a chip select.
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maxItems: 1
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rdwr-gpios:
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description:
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read/write select pin (referred to as RDWR_B in the manual)
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Optional gpio for if the bus controller does not provide this pin.
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maxItems: 1
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required:
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- compatible
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- reg
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- prog-gpios
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- done-gpios
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- init-gpios
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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fpga-mgr@8000000 {
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compatible = "xlnx,fpga-xc7s-selectmap";
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reg = <0x8000000 0x4>;
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prog-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
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init-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
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done-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
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csi-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
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rdwr-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
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};
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...
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