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bd60fcf276
Add binding for AC5 SoC. This SoC only supports NAND SDR timings up to mode 3 so a specific compatible value is needed. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230703035044.2063303-2-chris.packham@alliedtelesis.co.nz
227 lines
5.1 KiB
YAML
227 lines
5.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell NAND Flash Controller (NFC)
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maintainers:
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- Miquel Raynal <miquel.raynal@bootlin.com>
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properties:
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compatible:
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oneOf:
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- items:
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- const: marvell,armada-8k-nand-controller
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- const: marvell,armada370-nand-controller
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- enum:
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- marvell,ac5-nand-controller
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- marvell,armada370-nand-controller
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- marvell,pxa3xx-nand-controller
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- description: legacy bindings
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deprecated: true
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enum:
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- marvell,armada-8k-nand
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- marvell,armada370-nand
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- marvell,pxa3xx-nand
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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description:
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Shall reference the NAND controller clocks, the second one is
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is only needed for the Armada 7K/8K SoCs
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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items:
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- const: core
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- const: reg
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dmas:
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maxItems: 1
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dma-names:
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items:
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- const: data
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marvell,system-controller:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: Syscon node that handles NAND controller related registers
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patternProperties:
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"^nand@[a-f0-9]$":
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type: object
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$ref: raw-nand-chip.yaml
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properties:
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reg:
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minimum: 0
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maximum: 3
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nand-rb:
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items:
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- minimum: 0
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maximum: 1
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nand-ecc-step-size:
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const: 512
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nand-ecc-strength:
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enum: [1, 4, 8, 12, 16]
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nand-ecc-mode:
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const: hw
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marvell,nand-keep-config:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Orders the driver not to take the timings from the core and
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leaving them completely untouched. Bootloader timings will then
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be used.
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marvell,nand-enable-arbiter:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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To enable the arbiter, all boards blindly used it,
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this bit was set by the bootloader for many boards and even if
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it is marked reserved in several datasheets, it might be needed to set
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it (otherwise it is harmless).
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deprecated: true
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required:
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- reg
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- nand-rb
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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allOf:
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- $ref: nand-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: marvell,pxa3xx-nand-controller
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then:
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required:
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- dmas
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- dma-names
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- if:
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properties:
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compatible:
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contains:
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const: marvell,armada-8k-nand-controller
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then:
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properties:
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clocks:
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minItems: 2
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clock-names:
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minItems: 2
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required:
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- marvell,system-controller
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else:
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properties:
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clocks:
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minItems: 1
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clock-names:
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minItems: 1
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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nand_controller: nand-controller@d0000 {
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compatible = "marvell,armada370-nand-controller";
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reg = <0xd0000 0x54>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&coredivclk 0>;
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nand@0 {
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reg = <0>;
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label = "main-storage";
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nand-rb = <0>;
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nand-ecc-mode = "hw";
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marvell,nand-keep-config;
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nand-on-flash-bbt;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Rootfs";
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reg = <0x00000000 0x40000000>;
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};
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};
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};
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};
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- |
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cp0_nand_controller: nand-controller@720000 {
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compatible = "marvell,armada-8k-nand-controller",
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"marvell,armada370-nand-controller";
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reg = <0x720000 0x54>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core", "reg";
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clocks = <&cp0_clk 1 2>,
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<&cp0_clk 1 17>;
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marvell,system-controller = <&cp0_syscon0>;
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nand@0 {
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reg = <0>;
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label = "main-storage";
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nand-rb = <0>;
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nand-ecc-mode = "hw";
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nand-ecc-strength = <8>;
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nand-ecc-step-size = <512>;
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};
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};
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- |
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nand-controller@43100000 {
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compatible = "marvell,pxa3xx-nand-controller";
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reg = <0x43100000 90>;
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interrupts = <45>;
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clocks = <&clks 1>;
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clock-names = "core";
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dmas = <&pdma 97 3>;
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dma-names = "data";
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#address-cells = <1>;
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#size-cells = <0>;
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nand@0 {
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reg = <0>;
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nand-rb = <0>;
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nand-ecc-mode = "hw";
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marvell,nand-keep-config;
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};
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};
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...
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