306 lines
9.0 KiB
YAML
306 lines
9.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/marvell,pp2.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell CN913X / Marvell Armada 375, 7K, 8K Ethernet Controller
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maintainers:
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- Marcin Wojtas <mw@semihalf.com>
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- Russell King <linux@armlinux.org>
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description: |
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Marvell Armada 375 Ethernet Controller (PPv2.1)
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Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
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Marvell CN913X Ethernet Controller (PPv2.3)
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properties:
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compatible:
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enum:
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- marvell,armada-375-pp2
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- marvell,armada-7k-pp22
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reg:
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minItems: 3
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maxItems: 4
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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clocks:
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minItems: 2
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items:
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- description: main controller clock
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- description: GOP clock
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- description: MG clock
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- description: MG Core clock
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- description: AXI clock
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clock-names:
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minItems: 2
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items:
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- const: pp_clk
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- const: gop_clk
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- const: mg_clk
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- const: mg_core_clk
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- const: axi_clk
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dma-coherent: true
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marvell,system-controller:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: a phandle to the system controller.
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patternProperties:
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'^(ethernet-)?port@[0-2]$':
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type: object
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description: subnode for each ethernet port.
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$ref: ethernet-controller.yaml#
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unevaluatedProperties: false
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properties:
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reg:
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description: ID of the port from the MAC point of view.
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maximum: 2
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interrupts:
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minItems: 1
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maxItems: 10
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description: interrupt(s) for the port
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interrupt-names:
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minItems: 1
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items:
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- const: hif0
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- const: hif1
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- const: hif2
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- const: hif3
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- const: hif4
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- const: hif5
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- const: hif6
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- const: hif7
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- const: hif8
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- const: link
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description: >
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if more than a single interrupt for is given, must be the
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name associated to the interrupts listed. Valid names are:
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"hifX", with X in [0..8], and "link". The names "tx-cpu0",
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"tx-cpu1", "tx-cpu2", "tx-cpu3" and "rx-shared" are supported
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for backward compatibility but shouldn't be used for new
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additions.
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phys:
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minItems: 1
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maxItems: 2
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description: >
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Generic PHY, providing SerDes connectivity. For most modes,
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one lane is sufficient, but some (e.g. RXAUI) may require two.
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phy-mode:
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enum:
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- gmii
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- sgmii
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- rgmii-id
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- 1000base-x
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- 2500base-x
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- 5gbase-r
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- rxaui
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- 10gbase-r
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port-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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deprecated: true
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description: >
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ID of the port from the MAC point of view.
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Legacy binding for backward compatibility.
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marvell,loopback:
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$ref: /schemas/types.yaml#/definitions/flag
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description: port is loopback mode.
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gop-port-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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only for marvell,armada-7k-pp22, ID of the port from the
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GOP (Group Of Ports) point of view. This ID is used to index the
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per-port registers in the second register area.
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required:
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- reg
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- interrupts
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- phy-mode
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- port-id
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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allOf:
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- if:
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properties:
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compatible:
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const: marvell,armada-7k-pp22
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then:
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properties:
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reg:
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items:
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- description: Packet Processor registers
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- description: Networking interfaces registers
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- description: CM3 address space used for TX Flow Control
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clocks:
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minItems: 5
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clock-names:
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minItems: 5
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patternProperties:
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'^(ethernet-)?port@[0-2]$':
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required:
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- gop-port-id
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required:
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- marvell,system-controller
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else:
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properties:
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reg:
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items:
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- description: Packet Processor registers
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- description: LMS registers
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- description: Register area per eth0
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- description: Register area per eth1
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clocks:
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maxItems: 2
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clock-names:
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maxItems: 2
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patternProperties:
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'^(ethernet-)?port@[0-1]$':
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properties:
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reg:
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maximum: 1
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gop-port-id: false
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additionalProperties: false
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examples:
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- |
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// For Armada 375 variant
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#include <dt-bindings/interrupt-controller/mvebu-icu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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ethernet@f0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,armada-375-pp2";
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reg = <0xf0000 0xa000>,
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<0xc0000 0x3060>,
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<0xc4000 0x100>,
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<0xc5000 0x100>;
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clocks = <&gateclk 3>, <&gateclk 19>;
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clock-names = "pp_clk", "gop_clk";
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ethernet-port@0 {
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0>;
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port-id = <0>; /* For backward compatibility. */
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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ethernet-port@1 {
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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reg = <1>;
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port-id = <1>; /* For backward compatibility. */
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phy = <&phy3>;
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phy-mode = "gmii";
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};
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};
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- |
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// For Armada 7k/8k and Cn913x variants
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#include <dt-bindings/interrupt-controller/mvebu-icu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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ethernet@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,armada-7k-pp22";
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reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
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clocks = <&cp0_clk 1 3>, <&cp0_clk 1 9>,
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<&cp0_clk 1 5>, <&cp0_clk 1 6>, <&cp0_clk 1 18>;
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clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk";
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marvell,system-controller = <&cp0_syscon0>;
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ethernet-port@0 {
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interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 59 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 63 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 67 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 71 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
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"hif5", "hif6", "hif7", "hif8", "link";
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phy-mode = "10gbase-r";
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phys = <&cp0_comphy4 0>;
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reg = <0>;
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port-id = <0>; /* For backward compatibility. */
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gop-port-id = <0>;
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};
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ethernet-port@1 {
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interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 60 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 64 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 68 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 72 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
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"hif5", "hif6", "hif7", "hif8", "link";
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phy-mode = "rgmii-id";
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reg = <1>;
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port-id = <1>; /* For backward compatibility. */
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gop-port-id = <2>;
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};
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ethernet-port@2 {
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interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 61 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 65 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 69 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 73 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
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"hif5", "hif6", "hif7", "hif8", "link";
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phy-mode = "2500base-x";
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managed = "in-band-status";
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phys = <&cp0_comphy5 2>;
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sfp = <&sfp_eth3>;
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reg = <2>;
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port-id = <2>; /* For backward compatibility. */
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gop-port-id = <3>;
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};
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};
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