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652f2efa93
Convert the common MDIO mux bindings to DT schema. Drop the example from mdio-mux.yaml as mdio-mux-gpio.yaml has the same one. Cc: "David S. Miller" <davem@davemloft.net> Cc: Jakub Kicinski <kuba@kernel.org> Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Cc: Andrew Lunn <andrew@lunn.ch> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Russell King <linux@armlinux.org.uk> Cc: netdev@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20210526181411.2888516-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
135 lines
4 KiB
YAML
135 lines
4 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
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maintainers:
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- Andrew Lunn <andrew@lunn.ch>
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description:
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This is a special case of a MDIO bus multiplexer. One or more GPIO
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lines are used to control which child bus is connected.
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allOf:
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- $ref: /schemas/net/mdio-mux.yaml#
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properties:
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compatible:
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const: mdio-mux-gpio
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gpios:
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description:
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List of GPIOs used to control the multiplexer, least significant bit first.
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minItems: 1
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maxItems: 32
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required:
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- compatible
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- gpios
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unevaluatedProperties: false
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examples:
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- |
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/*
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An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
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pair of GPIO lines. Child busses 2 and 3 populated with 4
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PHYs each.
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*/
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mdio-mux {
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compatible = "mdio-mux-gpio";
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gpios = <&gpio1 3 0>, <&gpio1 4 0>;
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mdio-parent-bus = <&smi1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-phy@1 {
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reg = <1>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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ethernet-phy@2 {
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reg = <2>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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ethernet-phy@3 {
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reg = <3>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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ethernet-phy@4 {
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reg = <4>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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};
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mdio@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-phy@1 {
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reg = <1>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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ethernet-phy@2 {
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reg = <2>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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ethernet-phy@3 {
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reg = <3>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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ethernet-phy@4 {
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reg = <4>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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};
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};
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...
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