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652f2efa93
Convert the common MDIO mux bindings to DT schema. Drop the example from mdio-mux.yaml as mdio-mux-gpio.yaml has the same one. Cc: "David S. Miller" <davem@davemloft.net> Cc: Jakub Kicinski <kuba@kernel.org> Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Cc: Andrew Lunn <andrew@lunn.ch> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Russell King <linux@armlinux.org.uk> Cc: netdev@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20210526181411.2888516-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
78 lines
2.1 KiB
YAML
78 lines
2.1 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
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maintainers:
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- Andrew Lunn <andrew@lunn.ch>
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description: |+
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This is a special case of a MDIO bus multiplexer. A memory-mapped device,
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like an FPGA, is used to control which child bus is connected. The mdio-mux
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node must be a child of the memory-mapped device. The driver currently only
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supports devices with 8, 16 or 32-bit registers.
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allOf:
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- $ref: /schemas/net/mdio-mux.yaml#
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properties:
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compatible:
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items:
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- const: mdio-mux-mmioreg
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- const: mdio-mux
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reg:
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description: Contains the offset of the register that controls the bus
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multiplexer. The size field in the 'reg' property is the size of register,
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and must therefore be 1, 2, or 4.
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maxItems: 1
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mux-mask:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Contains an eight-bit mask that specifies which bits in the
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register control the actual bus multiplexer. The 'reg' property of each
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child mdio-mux node must be constrained by this mask.
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required:
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- compatible
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- reg
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- mux-mask
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unevaluatedProperties: false
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examples:
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- |
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mdio-mux@9 {
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compatible = "mdio-mux-mmioreg", "mdio-mux";
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mdio-parent-bus = <&xmdio0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <9 1>; // BRDCFG1
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mux-mask = <0x6>; // EMI2
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mdio@0 { // Slot 1 XAUI (FM2)
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy_xgmii_slot1: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <4>;
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};
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};
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mdio@2 { // Slot 2 XAUI (FM1)
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <4>;
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};
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};
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};
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...
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