mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-31 16:38:12 +00:00
e8069f5a8e
* Eager page splitting optimization for dirty logging, optionally
allowing for a VM to avoid the cost of hugepage splitting in the stage-2
fault path.
* Arm FF-A proxy for pKVM, allowing a pKVM host to safely interact with
services that live in the Secure world. pKVM intervenes on FF-A calls
to guarantee the host doesn't misuse memory donated to the hyp or a
pKVM guest.
* Support for running the split hypervisor with VHE enabled, known as
'hVHE' mode. This is extremely useful for testing the split
hypervisor on VHE-only systems, and paves the way for new use cases
that depend on having two TTBRs available at EL2.
* Generalized framework for configurable ID registers from userspace.
KVM/arm64 currently prevents arbitrary CPU feature set configuration
from userspace, but the intent is to relax this limitation and allow
userspace to select a feature set consistent with the CPU.
* Enable the use of Branch Target Identification (FEAT_BTI) in the
hypervisor.
* Use a separate set of pointer authentication keys for the hypervisor
when running in protected mode, as the host is untrusted at runtime.
* Ensure timer IRQs are consistently released in the init failure
paths.
* Avoid trapping CTR_EL0 on systems with Enhanced Virtualization Traps
(FEAT_EVT), as it is a register commonly read from userspace.
* Erratum workaround for the upcoming AmpereOne part, which has broken
hardware A/D state management.
RISC-V:
* Redirect AMO load/store misaligned traps to KVM guest
* Trap-n-emulate AIA in-kernel irqchip for KVM guest
* Svnapot support for KVM Guest
s390:
* New uvdevice secret API
* CMM selftest and fixes
* fix racy access to target CPU for diag 9c
x86:
* Fix missing/incorrect #GP checks on ENCLS
* Use standard mmu_notifier hooks for handling APIC access page
* Drop now unnecessary TR/TSS load after VM-Exit on AMD
* Print more descriptive information about the status of SEV and SEV-ES during
module load
* Add a test for splitting and reconstituting hugepages during and after
dirty logging
* Add support for CPU pinning in demand paging test
* Add support for AMD PerfMonV2, with a variety of cleanups and minor fixes
included along the way
* Add a "nx_huge_pages=never" option to effectively avoid creating NX hugepage
recovery threads (because nx_huge_pages=off can be toggled at runtime)
* Move handling of PAT out of MTRR code and dedup SVM+VMX code
* Fix output of PIC poll command emulation when there's an interrupt
* Add a maintainer's handbook to document KVM x86 processes, preferred coding
style, testing expectations, etc.
* Misc cleanups, fixes and comments
Generic:
* Miscellaneous bugfixes and cleanups
Selftests:
* Generate dependency files so that partial rebuilds work as expected
-----BEGIN PGP SIGNATURE-----
iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmSgHrIUHHBib256aW5p
QHJlZGhhdC5jb20ACgkQv/vSX3jHroORcAf+KkBlXwQMf+Q0Hy6Mfe0OtkKmh0Ae
6HJ6dsuMfOHhWv5kgukh+qvuGUGzHq+gpVKmZg2yP3h3cLHOLUAYMCDm+rjXyjsk
F4DbnJLfxq43Pe9PHRKFxxSecRcRYCNox0GD5UYL4PLKcH0FyfQrV+HVBK+GI8L3
FDzUcyJkR12Lcj1qf++7fsbzfOshL0AJPmidQCoc6wkLJpUEr/nYUqlI1Kx3YNuQ
LKmxFHS4l4/O/px3GKNDrLWDbrVlwciGIa3GZLS52PZdW3mAqT+cqcPcYK6SW71P
m1vE80VbNELX5q3YSRoOXtedoZ3Pk97LEmz/xQAsJ/jri0Z5Syk0Ok0m/Q==
=AMXp
-----END PGP SIGNATURE-----
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm updates from Paolo Bonzini:
"ARM64:
- Eager page splitting optimization for dirty logging, optionally
allowing for a VM to avoid the cost of hugepage splitting in the
stage-2 fault path.
- Arm FF-A proxy for pKVM, allowing a pKVM host to safely interact
with services that live in the Secure world. pKVM intervenes on
FF-A calls to guarantee the host doesn't misuse memory donated to
the hyp or a pKVM guest.
- Support for running the split hypervisor with VHE enabled, known as
'hVHE' mode. This is extremely useful for testing the split
hypervisor on VHE-only systems, and paves the way for new use cases
that depend on having two TTBRs available at EL2.
- Generalized framework for configurable ID registers from userspace.
KVM/arm64 currently prevents arbitrary CPU feature set
configuration from userspace, but the intent is to relax this
limitation and allow userspace to select a feature set consistent
with the CPU.
- Enable the use of Branch Target Identification (FEAT_BTI) in the
hypervisor.
- Use a separate set of pointer authentication keys for the
hypervisor when running in protected mode, as the host is untrusted
at runtime.
- Ensure timer IRQs are consistently released in the init failure
paths.
- Avoid trapping CTR_EL0 on systems with Enhanced Virtualization
Traps (FEAT_EVT), as it is a register commonly read from userspace.
- Erratum workaround for the upcoming AmpereOne part, which has
broken hardware A/D state management.
RISC-V:
- Redirect AMO load/store misaligned traps to KVM guest
- Trap-n-emulate AIA in-kernel irqchip for KVM guest
- Svnapot support for KVM Guest
s390:
- New uvdevice secret API
- CMM selftest and fixes
- fix racy access to target CPU for diag 9c
x86:
- Fix missing/incorrect #GP checks on ENCLS
- Use standard mmu_notifier hooks for handling APIC access page
- Drop now unnecessary TR/TSS load after VM-Exit on AMD
- Print more descriptive information about the status of SEV and
SEV-ES during module load
- Add a test for splitting and reconstituting hugepages during and
after dirty logging
- Add support for CPU pinning in demand paging test
- Add support for AMD PerfMonV2, with a variety of cleanups and minor
fixes included along the way
- Add a "nx_huge_pages=never" option to effectively avoid creating NX
hugepage recovery threads (because nx_huge_pages=off can be toggled
at runtime)
- Move handling of PAT out of MTRR code and dedup SVM+VMX code
- Fix output of PIC poll command emulation when there's an interrupt
- Add a maintainer's handbook to document KVM x86 processes,
preferred coding style, testing expectations, etc.
- Misc cleanups, fixes and comments
Generic:
- Miscellaneous bugfixes and cleanups
Selftests:
- Generate dependency files so that partial rebuilds work as
expected"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (153 commits)
Documentation/process: Add a maintainer handbook for KVM x86
Documentation/process: Add a label for the tip tree handbook's coding style
KVM: arm64: Fix misuse of KVM_ARM_VCPU_POWER_OFF bit index
RISC-V: KVM: Remove unneeded semicolon
RISC-V: KVM: Allow Svnapot extension for Guest/VM
riscv: kvm: define vcpu_sbi_ext_pmu in header
RISC-V: KVM: Expose IMSIC registers as attributes of AIA irqchip
RISC-V: KVM: Add in-kernel virtualization of AIA IMSIC
RISC-V: KVM: Expose APLIC registers as attributes of AIA irqchip
RISC-V: KVM: Add in-kernel emulation of AIA APLIC
RISC-V: KVM: Implement device interface for AIA irqchip
RISC-V: KVM: Skeletal in-kernel AIA irqchip support
RISC-V: KVM: Set kvm_riscv_aia_nr_hgei to zero
RISC-V: KVM: Add APLIC related defines
RISC-V: KVM: Add IMSIC related defines
RISC-V: KVM: Implement guest external interrupt line management
KVM: x86: Remove PRIx* definitions as they are solely for user space
s390/uv: Update query for secret-UVCs
s390/uv: replace scnprintf with sysfs_emit
s390/uvdevice: Add 'Lock Secret Store' UVC
...
258 lines
5.9 KiB
ArmAsm
258 lines
5.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Hypervisor stub
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*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/el2_setup.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_asm.h>
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#include <asm/ptrace.h>
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#include <asm/virt.h>
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.text
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.pushsection .hyp.text, "ax"
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.align 11
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SYM_CODE_START(__hyp_stub_vectors)
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ventry el2_sync_invalid // Synchronous EL2t
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ventry el2_irq_invalid // IRQ EL2t
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ventry el2_fiq_invalid // FIQ EL2t
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ventry el2_error_invalid // Error EL2t
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ventry elx_sync // Synchronous EL2h
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ventry el2_irq_invalid // IRQ EL2h
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ventry el2_fiq_invalid // FIQ EL2h
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ventry el2_error_invalid // Error EL2h
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ventry elx_sync // Synchronous 64-bit EL1
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ventry el1_irq_invalid // IRQ 64-bit EL1
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ventry el1_fiq_invalid // FIQ 64-bit EL1
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ventry el1_error_invalid // Error 64-bit EL1
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ventry el1_sync_invalid // Synchronous 32-bit EL1
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ventry el1_irq_invalid // IRQ 32-bit EL1
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ventry el1_fiq_invalid // FIQ 32-bit EL1
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ventry el1_error_invalid // Error 32-bit EL1
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SYM_CODE_END(__hyp_stub_vectors)
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.align 11
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SYM_CODE_START_LOCAL(elx_sync)
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cmp x0, #HVC_SET_VECTORS
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b.ne 1f
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msr vbar_el2, x1
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b 9f
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1: cmp x0, #HVC_FINALISE_EL2
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b.eq __finalise_el2
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2: cmp x0, #HVC_SOFT_RESTART
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b.ne 3f
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mov x0, x2
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mov x2, x4
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mov x4, x1
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mov x1, x3
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br x4 // no return
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3: cmp x0, #HVC_RESET_VECTORS
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beq 9f // Nothing to reset!
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/* Someone called kvm_call_hyp() against the hyp-stub... */
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mov_q x0, HVC_STUB_ERR
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eret
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9: mov x0, xzr
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eret
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SYM_CODE_END(elx_sync)
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SYM_CODE_START_LOCAL(__finalise_el2)
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finalise_el2_state
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// nVHE? No way! Give me the real thing!
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// Sanity check: MMU *must* be off
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mrs x1, sctlr_el2
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tbnz x1, #0, 1f
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// Needs to be VHE capable, obviously
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check_override id_aa64mmfr1 ID_AA64MMFR1_EL1_VH_SHIFT 0f 1f x1 x2
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0: // Check whether we only want the hypervisor to run VHE, not the kernel
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adr_l x1, arm64_sw_feature_override
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ldr x2, [x1, FTR_OVR_VAL_OFFSET]
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ldr x1, [x1, FTR_OVR_MASK_OFFSET]
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and x2, x2, x1
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ubfx x2, x2, #ARM64_SW_FEATURE_OVERRIDE_HVHE, #4
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cbz x2, 2f
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1: mov_q x0, HVC_STUB_ERR
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eret
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2:
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// Engage the VHE magic!
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mov_q x0, HCR_HOST_VHE_FLAGS
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msr hcr_el2, x0
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isb
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// Use the EL1 allocated stack, per-cpu offset
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mrs x0, sp_el1
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mov sp, x0
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mrs x0, tpidr_el1
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msr tpidr_el2, x0
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// FP configuration, vectors
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mrs_s x0, SYS_CPACR_EL12
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msr cpacr_el1, x0
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mrs_s x0, SYS_VBAR_EL12
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msr vbar_el1, x0
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// Use EL2 translations for SPE & TRBE and disable access from EL1
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mrs x0, mdcr_el2
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bic x0, x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
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bic x0, x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)
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msr mdcr_el2, x0
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// Transfer the MM state from EL1 to EL2
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mrs_s x0, SYS_TCR_EL12
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msr tcr_el1, x0
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mrs_s x0, SYS_TTBR0_EL12
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msr ttbr0_el1, x0
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mrs_s x0, SYS_TTBR1_EL12
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msr ttbr1_el1, x0
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mrs_s x0, SYS_MAIR_EL12
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msr mair_el1, x0
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mrs x1, REG_ID_AA64MMFR3_EL1
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ubfx x1, x1, #ID_AA64MMFR3_EL1_TCRX_SHIFT, #4
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cbz x1, .Lskip_tcr2
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mrs x0, REG_TCR2_EL12
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msr REG_TCR2_EL1, x0
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// Transfer permission indirection state
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mrs x1, REG_ID_AA64MMFR3_EL1
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ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
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cbz x1, .Lskip_indirection
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mrs x0, REG_PIRE0_EL12
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msr REG_PIRE0_EL1, x0
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mrs x0, REG_PIR_EL12
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msr REG_PIR_EL1, x0
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.Lskip_indirection:
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.Lskip_tcr2:
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isb
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// Hack the exception return to stay at EL2
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mrs x0, spsr_el1
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and x0, x0, #~PSR_MODE_MASK
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mov x1, #PSR_MODE_EL2h
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orr x0, x0, x1
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msr spsr_el1, x0
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b enter_vhe
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SYM_CODE_END(__finalise_el2)
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// At the point where we reach enter_vhe(), we run with
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// the MMU off (which is enforced by __finalise_el2()).
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// We thus need to be in the idmap, or everything will
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// explode when enabling the MMU.
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.pushsection .idmap.text, "ax"
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SYM_CODE_START_LOCAL(enter_vhe)
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// Invalidate TLBs before enabling the MMU
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tlbi vmalle1
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dsb nsh
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isb
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// Enable the EL2 S1 MMU, as set up from EL1
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mrs_s x0, SYS_SCTLR_EL12
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set_sctlr_el1 x0
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// Disable the EL1 S1 MMU for a good measure
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mov_q x0, INIT_SCTLR_EL1_MMU_OFF
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msr_s SYS_SCTLR_EL12, x0
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mov x0, xzr
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eret
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SYM_CODE_END(enter_vhe)
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.popsection
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.macro invalid_vector label
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SYM_CODE_START_LOCAL(\label)
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b \label
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SYM_CODE_END(\label)
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.endm
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invalid_vector el2_sync_invalid
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invalid_vector el2_irq_invalid
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invalid_vector el2_fiq_invalid
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invalid_vector el2_error_invalid
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invalid_vector el1_sync_invalid
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invalid_vector el1_irq_invalid
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invalid_vector el1_fiq_invalid
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invalid_vector el1_error_invalid
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.popsection
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/*
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* __hyp_set_vectors: Call this after boot to set the initial hypervisor
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* vectors as part of hypervisor installation. On an SMP system, this should
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* be called on each CPU.
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*
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* x0 must be the physical address of the new vector table, and must be
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* 2KB aligned.
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*
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* Before calling this, you must check that the stub hypervisor is installed
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* everywhere, by waiting for any secondary CPUs to be brought up and then
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* checking that is_hyp_mode_available() is true.
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*
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* If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
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* something else went wrong... in such cases, trying to install a new
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* hypervisor is unlikely to work as desired.
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*
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* When you call into your shiny new hypervisor, sp_el2 will contain junk,
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* so you will need to set that to something sensible at the new hypervisor's
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* initialisation entry point.
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*/
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SYM_FUNC_START(__hyp_set_vectors)
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mov x1, x0
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mov x0, #HVC_SET_VECTORS
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hvc #0
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ret
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SYM_FUNC_END(__hyp_set_vectors)
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SYM_FUNC_START(__hyp_reset_vectors)
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mov x0, #HVC_RESET_VECTORS
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hvc #0
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ret
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SYM_FUNC_END(__hyp_reset_vectors)
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/*
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* Entry point to finalise EL2 and switch to VHE if deemed capable
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*
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* w0: boot mode, as returned by init_kernel_el()
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*/
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SYM_FUNC_START(finalise_el2)
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// Need to have booted at EL2
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cmp w0, #BOOT_CPU_MODE_EL2
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b.ne 1f
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// and still be at EL1
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mrs x0, CurrentEL
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cmp x0, #CurrentEL_EL1
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b.ne 1f
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mov x0, #HVC_FINALISE_EL2
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hvc #0
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1:
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ret
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SYM_FUNC_END(finalise_el2)
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