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![Linus Torvalds](/assets/img/avatar_default.png)
Pull crypto update from Herbert Xu: "Here is the crypto update for 4.2: API: - Convert RNG interface to new style. - New AEAD interface with one SG list for AD and plain/cipher text. All external AEAD users have been converted. - New asymmetric key interface (akcipher). Algorithms: - Chacha20, Poly1305 and RFC7539 support. - New RSA implementation. - Jitter RNG. - DRBG is now seeded with both /dev/random and Jitter RNG. If kernel pool isn't ready then DRBG will be reseeded when it is. - DRBG is now the default crypto API RNG, replacing krng. - 842 compression (previously part of powerpc nx driver). Drivers: - Accelerated SHA-512 for arm64. - New Marvell CESA driver that supports DMA and more algorithms. - Updated powerpc nx 842 support. - Added support for SEC1 hardware to talitos" * git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (292 commits) crypto: marvell/cesa - remove COMPILE_TEST dependency crypto: algif_aead - Temporarily disable all AEAD algorithms crypto: af_alg - Forbid the use internal algorithms crypto: echainiv - Only hold RNG during initialisation crypto: seqiv - Add compatibility support without RNG crypto: eseqiv - Offer normal cipher functionality without RNG crypto: chainiv - Offer normal cipher functionality without RNG crypto: user - Add CRYPTO_MSG_DELRNG crypto: user - Move cryptouser.h to uapi crypto: rng - Do not free default RNG when it becomes unused crypto: skcipher - Allow givencrypt to be NULL crypto: sahara - propagate the error on clk_disable_unprepare() failure crypto: rsa - fix invalid select for AKCIPHER crypto: picoxcell - Update to the current clk API crypto: nx - Check for bogus firmware properties crypto: marvell/cesa - add DT bindings documentation crypto: marvell/cesa - add support for Kirkwood and Dove SoCs crypto: marvell/cesa - add support for Orion SoCs crypto: marvell/cesa - add allhwsupport module parameter crypto: marvell/cesa - add support for all armada SoCs ...
198 lines
5.1 KiB
C
198 lines
5.1 KiB
C
/**
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* AES CBC routines supporting VMX instructions on the Power 8
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*
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* Copyright (C) 2015 International Business Machines Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 only.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Author: Marcelo Henrique Cerri <mhcerri@br.ibm.com>
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*/
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#include <linux/types.h>
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#include <linux/err.h>
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#include <linux/crypto.h>
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#include <linux/delay.h>
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#include <linux/hardirq.h>
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#include <asm/switch_to.h>
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#include <crypto/aes.h>
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#include <crypto/scatterwalk.h>
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#include "aesp8-ppc.h"
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struct p8_aes_cbc_ctx {
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struct crypto_blkcipher *fallback;
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struct aes_key enc_key;
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struct aes_key dec_key;
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};
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static int p8_aes_cbc_init(struct crypto_tfm *tfm)
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{
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const char *alg;
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struct crypto_blkcipher *fallback;
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struct p8_aes_cbc_ctx *ctx = crypto_tfm_ctx(tfm);
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if (!(alg = crypto_tfm_alg_name(tfm))) {
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printk(KERN_ERR "Failed to get algorithm name.\n");
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return -ENOENT;
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}
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fallback =
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crypto_alloc_blkcipher(alg, 0, CRYPTO_ALG_NEED_FALLBACK);
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if (IS_ERR(fallback)) {
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printk(KERN_ERR
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"Failed to allocate transformation for '%s': %ld\n",
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alg, PTR_ERR(fallback));
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return PTR_ERR(fallback);
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}
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printk(KERN_INFO "Using '%s' as fallback implementation.\n",
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crypto_tfm_alg_driver_name((struct crypto_tfm *) fallback));
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crypto_blkcipher_set_flags(
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fallback,
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crypto_blkcipher_get_flags((struct crypto_blkcipher *)tfm));
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ctx->fallback = fallback;
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return 0;
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}
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static void p8_aes_cbc_exit(struct crypto_tfm *tfm)
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{
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struct p8_aes_cbc_ctx *ctx = crypto_tfm_ctx(tfm);
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if (ctx->fallback) {
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crypto_free_blkcipher(ctx->fallback);
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ctx->fallback = NULL;
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}
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}
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static int p8_aes_cbc_setkey(struct crypto_tfm *tfm, const u8 *key,
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unsigned int keylen)
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{
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int ret;
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struct p8_aes_cbc_ctx *ctx = crypto_tfm_ctx(tfm);
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preempt_disable();
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pagefault_disable();
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enable_kernel_altivec();
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ret = aes_p8_set_encrypt_key(key, keylen * 8, &ctx->enc_key);
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ret += aes_p8_set_decrypt_key(key, keylen * 8, &ctx->dec_key);
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pagefault_enable();
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preempt_enable();
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ret += crypto_blkcipher_setkey(ctx->fallback, key, keylen);
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return ret;
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}
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static int p8_aes_cbc_encrypt(struct blkcipher_desc *desc,
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struct scatterlist *dst,
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struct scatterlist *src, unsigned int nbytes)
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{
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int ret;
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struct blkcipher_walk walk;
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struct p8_aes_cbc_ctx *ctx =
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crypto_tfm_ctx(crypto_blkcipher_tfm(desc->tfm));
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struct blkcipher_desc fallback_desc = {
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.tfm = ctx->fallback,
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.info = desc->info,
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.flags = desc->flags
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};
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if (in_interrupt()) {
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ret = crypto_blkcipher_encrypt(&fallback_desc, dst, src,
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nbytes);
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} else {
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preempt_disable();
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pagefault_disable();
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enable_kernel_altivec();
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blkcipher_walk_init(&walk, dst, src, nbytes);
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ret = blkcipher_walk_virt(desc, &walk);
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while ((nbytes = walk.nbytes)) {
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aes_p8_cbc_encrypt(walk.src.virt.addr,
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walk.dst.virt.addr,
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nbytes & AES_BLOCK_MASK,
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&ctx->enc_key, walk.iv, 1);
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nbytes &= AES_BLOCK_SIZE - 1;
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ret = blkcipher_walk_done(desc, &walk, nbytes);
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}
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pagefault_enable();
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preempt_enable();
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}
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return ret;
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}
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static int p8_aes_cbc_decrypt(struct blkcipher_desc *desc,
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struct scatterlist *dst,
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struct scatterlist *src, unsigned int nbytes)
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{
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int ret;
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struct blkcipher_walk walk;
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struct p8_aes_cbc_ctx *ctx =
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crypto_tfm_ctx(crypto_blkcipher_tfm(desc->tfm));
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struct blkcipher_desc fallback_desc = {
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.tfm = ctx->fallback,
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.info = desc->info,
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.flags = desc->flags
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};
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if (in_interrupt()) {
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ret = crypto_blkcipher_decrypt(&fallback_desc, dst, src,
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nbytes);
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} else {
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preempt_disable();
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pagefault_disable();
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enable_kernel_altivec();
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blkcipher_walk_init(&walk, dst, src, nbytes);
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ret = blkcipher_walk_virt(desc, &walk);
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while ((nbytes = walk.nbytes)) {
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aes_p8_cbc_encrypt(walk.src.virt.addr,
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walk.dst.virt.addr,
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nbytes & AES_BLOCK_MASK,
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&ctx->dec_key, walk.iv, 0);
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nbytes &= AES_BLOCK_SIZE - 1;
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ret = blkcipher_walk_done(desc, &walk, nbytes);
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}
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pagefault_enable();
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preempt_enable();
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}
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return ret;
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}
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struct crypto_alg p8_aes_cbc_alg = {
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.cra_name = "cbc(aes)",
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.cra_driver_name = "p8_aes_cbc",
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.cra_module = THIS_MODULE,
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.cra_priority = 1000,
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.cra_type = &crypto_blkcipher_type,
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.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | CRYPTO_ALG_NEED_FALLBACK,
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.cra_alignmask = 0,
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.cra_blocksize = AES_BLOCK_SIZE,
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.cra_ctxsize = sizeof(struct p8_aes_cbc_ctx),
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.cra_init = p8_aes_cbc_init,
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.cra_exit = p8_aes_cbc_exit,
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.cra_blkcipher = {
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.ivsize = 0,
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.min_keysize = AES_MIN_KEY_SIZE,
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.max_keysize = AES_MAX_KEY_SIZE,
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.setkey = p8_aes_cbc_setkey,
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.encrypt = p8_aes_cbc_encrypt,
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.decrypt = p8_aes_cbc_decrypt,
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},
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};
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