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25824d52ca
In most of hisilicon SOCs, reset controller and clock provider are combined together as a block named CRG (Clock and Reset Generator). This patch mainly implements the reset function. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
36 lines
1.1 KiB
C
36 lines
1.1 KiB
C
/*
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* Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __HISI_RESET_H
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#define __HISI_RESET_H
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struct device_node;
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struct hisi_reset_controller;
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#ifdef CONFIG_RESET_CONTROLLER
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struct hisi_reset_controller *hisi_reset_init(struct device_node *np);
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void hisi_reset_exit(struct hisi_reset_controller *rstc);
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#else
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static inline hisi_reset_controller *hisi_reset_init(struct device_node *np)
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{
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return 0;
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}
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static inline void hisi_reset_exit(struct hisi_reset_controller *rstc)
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{}
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#endif
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#endif /* __HISI_RESET_H */
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