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![Maxime Ripard](/assets/img/avatar_default.png)
The A10 SoCs and its relatives has a special clock controller to drive the display engines (both frontend and backend), that have a lot in common with the clock to drive the first TCON channel. Add a driver to support both. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> [sboyd@codeaurora.org: Silence variable sized array warning] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
261 lines
6.2 KiB
C
261 lines
6.2 KiB
C
/*
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* Copyright 2015 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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struct sun4i_a10_display_clk_data {
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bool has_div;
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u8 num_rst;
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u8 parents;
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u8 offset_en;
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u8 offset_div;
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u8 offset_mux;
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u8 offset_rst;
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u8 width_div;
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u8 width_mux;
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};
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struct reset_data {
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void __iomem *reg;
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spinlock_t *lock;
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struct reset_controller_dev rcdev;
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u8 offset;
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};
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static DEFINE_SPINLOCK(sun4i_a10_display_lock);
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static inline struct reset_data *rcdev_to_reset_data(struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct reset_data, rcdev);
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};
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static int sun4i_a10_display_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct reset_data *data = rcdev_to_reset_data(rcdev);
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(data->lock, flags);
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reg = readl(data->reg);
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writel(reg & ~BIT(data->offset + id), data->reg);
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spin_unlock_irqrestore(data->lock, flags);
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return 0;
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}
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static int sun4i_a10_display_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct reset_data *data = rcdev_to_reset_data(rcdev);
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(data->lock, flags);
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reg = readl(data->reg);
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writel(reg | BIT(data->offset + id), data->reg);
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spin_unlock_irqrestore(data->lock, flags);
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return 0;
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}
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static int sun4i_a10_display_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct reset_data *data = rcdev_to_reset_data(rcdev);
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return !(readl(data->reg) & BIT(data->offset + id));
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}
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static const struct reset_control_ops sun4i_a10_display_reset_ops = {
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.assert = sun4i_a10_display_assert,
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.deassert = sun4i_a10_display_deassert,
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.status = sun4i_a10_display_status,
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};
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static int sun4i_a10_display_reset_xlate(struct reset_controller_dev *rcdev,
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const struct of_phandle_args *spec)
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{
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/* We only have a single reset signal */
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return 0;
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}
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static void __init sun4i_a10_display_init(struct device_node *node,
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const struct sun4i_a10_display_clk_data *data)
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{
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const char *parents[4];
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const char *clk_name = node->name;
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struct reset_data *reset_data;
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struct clk_divider *div = NULL;
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struct clk_gate *gate;
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struct resource res;
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struct clk_mux *mux;
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void __iomem *reg;
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struct clk *clk;
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int ret;
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of_property_read_string(node, "clock-output-names", &clk_name);
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (IS_ERR(reg)) {
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pr_err("%s: Could not map the clock registers\n", clk_name);
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return;
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}
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ret = of_clk_parent_fill(node, parents, data->parents);
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if (ret != data->parents) {
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pr_err("%s: Could not retrieve the parents\n", clk_name);
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goto unmap;
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}
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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goto unmap;
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mux->reg = reg;
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mux->shift = data->offset_mux;
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mux->mask = (1 << data->width_mux) - 1;
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mux->lock = &sun4i_a10_display_lock;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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goto free_mux;
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gate->reg = reg;
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gate->bit_idx = data->offset_en;
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gate->lock = &sun4i_a10_display_lock;
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if (data->has_div) {
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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goto free_gate;
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div->reg = reg;
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div->shift = data->offset_div;
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div->width = data->width_div;
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div->lock = &sun4i_a10_display_lock;
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}
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clk = clk_register_composite(NULL, clk_name,
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parents, data->parents,
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&mux->hw, &clk_mux_ops,
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data->has_div ? &div->hw : NULL,
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data->has_div ? &clk_divider_ops : NULL,
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&gate->hw, &clk_gate_ops,
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0);
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if (IS_ERR(clk)) {
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pr_err("%s: Couldn't register the clock\n", clk_name);
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goto free_div;
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}
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ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
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if (ret) {
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pr_err("%s: Couldn't register DT provider\n", clk_name);
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goto free_clk;
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}
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if (!data->num_rst)
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return;
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reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
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if (!reset_data)
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goto free_of_clk;
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reset_data->reg = reg;
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reset_data->offset = data->offset_rst;
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reset_data->lock = &sun4i_a10_display_lock;
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reset_data->rcdev.nr_resets = data->num_rst;
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reset_data->rcdev.ops = &sun4i_a10_display_reset_ops;
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reset_data->rcdev.of_node = node;
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if (data->num_rst == 1) {
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reset_data->rcdev.of_reset_n_cells = 0;
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reset_data->rcdev.of_xlate = &sun4i_a10_display_reset_xlate;
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} else {
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reset_data->rcdev.of_reset_n_cells = 1;
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}
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if (reset_controller_register(&reset_data->rcdev)) {
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pr_err("%s: Couldn't register the reset controller\n",
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clk_name);
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goto free_reset;
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}
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return;
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free_reset:
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kfree(reset_data);
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free_of_clk:
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of_clk_del_provider(node);
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free_clk:
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clk_unregister_composite(clk);
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free_div:
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kfree(div);
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free_gate:
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kfree(gate);
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free_mux:
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kfree(mux);
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unmap:
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iounmap(reg);
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of_address_to_resource(node, 0, &res);
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release_mem_region(res.start, resource_size(&res));
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}
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static const struct sun4i_a10_display_clk_data sun4i_a10_tcon_ch0_data __initconst = {
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.num_rst = 2,
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.parents = 4,
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.offset_en = 31,
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.offset_rst = 29,
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.offset_mux = 24,
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.width_mux = 2,
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};
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static void __init sun4i_a10_tcon_ch0_setup(struct device_node *node)
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{
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sun4i_a10_display_init(node, &sun4i_a10_tcon_ch0_data);
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}
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CLK_OF_DECLARE(sun4i_a10_tcon_ch0, "allwinner,sun4i-a10-tcon-ch0-clk",
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sun4i_a10_tcon_ch0_setup);
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static const struct sun4i_a10_display_clk_data sun4i_a10_display_data __initconst = {
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.has_div = true,
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.num_rst = 1,
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.parents = 3,
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.offset_en = 31,
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.offset_rst = 30,
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.offset_mux = 24,
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.offset_div = 0,
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.width_mux = 2,
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.width_div = 4,
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};
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static void __init sun4i_a10_display_setup(struct device_node *node)
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{
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sun4i_a10_display_init(node, &sun4i_a10_display_data);
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}
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CLK_OF_DECLARE(sun4i_a10_display, "allwinner,sun4i-a10-display-clk",
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sun4i_a10_display_setup);
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