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![Stephen Boyd](/assets/img/avatar_default.png)
As usual, a bunch of clocks patches for 4.7, mostly fixes and cleanups, and display-related clocks. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXI4/UAAoJEBx+YmzsjxAgJ9sP/iAKVRDJt/ng0Zw+niGC8EMZ AdqXCSbRj7bwnIyT+0ETEFIhaUTXVEg0wIfEQxPKIMOatL51OlR0Iuwviji43IeF oJUDQHSuKOZav7mlLKuEQJIOQBlqbMqjSecFyPN7yqRS9+qD+bDxWE54wXxapXPN QT/RT7662cSUWzmeUFE5OcBd8AIHQp32ozeWFA7kezfExUqQXHopFi98e0erba+x Z74cfC7aNOce3BcgpiyY0UdfHWIGZxkTEFp6KELX92gCrGVghQ+SjOTyp6FIcU/N Y+3BEsjMEByRfhxokKdmReoOAHlHJOmPlERa7vUqsksbEHYtNbbQxRMag76R00hI BdOASfvHcJVSeQQWKgOcdHoHCZcNubgDMjqv0aRY1ZX7MeVg1qxw+XEhsunUTNay Ifjq2qRLY2dGOioUk9adCorr3Z+Of9uPjB1VTQSbrKgJLe7fMdXp8ww6iNxQZ9eo x5JtjaJ2sREFQNGK8WzpImCJ5g6Oa0GQ7C4Lg/Y3obFRnsBiGDKLJDwmbHkhO/ZK i8N7AXIum0k+Tad8ndLLTahKJ4iH46E2RKDbieCzRIW0oqnB+nAzsm4a2SG3AJFR hB11sL3WCugDDJHCQvzCzdadHXSOYJC3g30r/WC7jr6ri0c7IHXQ0OHHhF1d36Ms rzWKUbSyINwTXtjijfiS =ttF/ -----END PGP SIGNATURE----- Merge tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clock driver updates from Maxime Ripard: As usual, a bunch of clocks patches for 4.7, mostly fixes and cleanups, and display-related clocks. * tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi: Let divs clocks read the base factor clock name from devicetree clk: sunxi: Add TCON channel1 clock clk: sunxi: Add PLL3 clock dt-bindings: clk: sun5i: add DRAM gates compatible clk: sunxi: Use resource_size clk: sunxi: Add sun6i/8i display support clk: sunxi: mod1 clock should modify it's parent
221 lines
5.7 KiB
C
221 lines
5.7 KiB
C
/*
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* Copyright 2015 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/reset.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#define SUN9I_MMC_WIDTH 4
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#define SUN9I_MMC_GATE_BIT 16
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#define SUN9I_MMC_RESET_BIT 18
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struct sun9i_mmc_clk_data {
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spinlock_t lock;
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void __iomem *membase;
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struct clk *clk;
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struct reset_control *reset;
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struct clk_onecell_data clk_data;
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struct reset_controller_dev rcdev;
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};
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static int sun9i_mmc_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct sun9i_mmc_clk_data *data = container_of(rcdev,
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struct sun9i_mmc_clk_data,
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rcdev);
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unsigned long flags;
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void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
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u32 val;
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clk_prepare_enable(data->clk);
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spin_lock_irqsave(&data->lock, flags);
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val = readl(reg);
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writel(val & ~BIT(SUN9I_MMC_RESET_BIT), reg);
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spin_unlock_irqrestore(&data->lock, flags);
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clk_disable_unprepare(data->clk);
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return 0;
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}
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static int sun9i_mmc_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct sun9i_mmc_clk_data *data = container_of(rcdev,
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struct sun9i_mmc_clk_data,
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rcdev);
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unsigned long flags;
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void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
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u32 val;
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clk_prepare_enable(data->clk);
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spin_lock_irqsave(&data->lock, flags);
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val = readl(reg);
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writel(val | BIT(SUN9I_MMC_RESET_BIT), reg);
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spin_unlock_irqrestore(&data->lock, flags);
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clk_disable_unprepare(data->clk);
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return 0;
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}
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static const struct reset_control_ops sun9i_mmc_reset_ops = {
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.assert = sun9i_mmc_reset_assert,
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.deassert = sun9i_mmc_reset_deassert,
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};
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static int sun9i_a80_mmc_config_clk_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct sun9i_mmc_clk_data *data;
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struct clk_onecell_data *clk_data;
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const char *clk_name = np->name;
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const char *clk_parent;
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struct resource *r;
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int count, i, ret;
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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spin_lock_init(&data->lock);
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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/* one clock/reset pair per word */
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count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH);
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data->membase = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(data->membase))
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return PTR_ERR(data->membase);
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clk_data = &data->clk_data;
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clk_data->clk_num = count;
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clk_data->clks = devm_kcalloc(&pdev->dev, count, sizeof(struct clk *),
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GFP_KERNEL);
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if (!clk_data->clks)
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return -ENOMEM;
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data->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(data->clk)) {
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dev_err(&pdev->dev, "Could not get clock\n");
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return PTR_ERR(data->clk);
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}
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data->reset = devm_reset_control_get(&pdev->dev, NULL);
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if (IS_ERR(data->reset)) {
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dev_err(&pdev->dev, "Could not get reset control\n");
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return PTR_ERR(data->reset);
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}
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ret = reset_control_deassert(data->reset);
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if (ret) {
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dev_err(&pdev->dev, "Reset deassert err %d\n", ret);
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return ret;
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}
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clk_parent = __clk_get_name(data->clk);
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for (i = 0; i < count; i++) {
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of_property_read_string_index(np, "clock-output-names",
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i, &clk_name);
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clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
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clk_parent, 0,
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data->membase + SUN9I_MMC_WIDTH * i,
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SUN9I_MMC_GATE_BIT, 0,
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&data->lock);
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if (IS_ERR(clk_data->clks[i])) {
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ret = PTR_ERR(clk_data->clks[i]);
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goto err_clk_register;
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}
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}
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ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
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if (ret)
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goto err_clk_provider;
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data->rcdev.owner = THIS_MODULE;
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data->rcdev.nr_resets = count;
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data->rcdev.ops = &sun9i_mmc_reset_ops;
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data->rcdev.of_node = pdev->dev.of_node;
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ret = reset_controller_register(&data->rcdev);
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if (ret)
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goto err_rc_reg;
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platform_set_drvdata(pdev, data);
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return 0;
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err_rc_reg:
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of_clk_del_provider(np);
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err_clk_provider:
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for (i = 0; i < count; i++)
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clk_unregister(clk_data->clks[i]);
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err_clk_register:
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reset_control_assert(data->reset);
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return ret;
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}
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static int sun9i_a80_mmc_config_clk_remove(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct sun9i_mmc_clk_data *data = platform_get_drvdata(pdev);
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struct clk_onecell_data *clk_data = &data->clk_data;
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int i;
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reset_controller_unregister(&data->rcdev);
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of_clk_del_provider(np);
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for (i = 0; i < clk_data->clk_num; i++)
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clk_unregister(clk_data->clks[i]);
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reset_control_assert(data->reset);
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return 0;
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}
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static const struct of_device_id sun9i_a80_mmc_config_clk_dt_ids[] = {
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{ .compatible = "allwinner,sun9i-a80-mmc-config-clk" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, sun9i_a80_mmc_config_clk_dt_ids);
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static struct platform_driver sun9i_a80_mmc_config_clk_driver = {
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.driver = {
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.name = "sun9i-a80-mmc-config-clk",
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.of_match_table = sun9i_a80_mmc_config_clk_dt_ids,
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},
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.probe = sun9i_a80_mmc_config_clk_probe,
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.remove = sun9i_a80_mmc_config_clk_remove,
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};
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module_platform_driver(sun9i_a80_mmc_config_clk_driver);
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MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
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MODULE_DESCRIPTION("Allwinner A80 MMC clock/reset Driver");
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MODULE_LICENSE("GPL v2");
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