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4bd1d80efb
Current implementation of update_mmu_cache function performs local TLB
flush. It does not take into account ASID information. Besides, it does
not take into account other harts currently running the same mm context
or possible migration of the running context to other harts. Meanwhile
TLB flush is not performed for every context switch if ASID support
is enabled.
Patch [1] proposed to add ASID support to update_mmu_cache to avoid
flushing local TLB entirely. This patch takes into account other
harts currently running the same mm context as well as possible
migration of this context to other harts.
For this purpose the approach from flush_icache_mm is reused. Remote
harts currently running the same mm context are informed via SBI calls
that they need to flush their local TLBs. All the other harts are marked
as needing a deferred TLB flush when this mm context runs on them.
[1] https://lore.kernel.org/linux-riscv/20220821013926.8968-1-tjytimi@163.com/
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Fixes: 65d4b9c530 ("RISC-V: Implement ASID allocator")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/linux-riscv/20220829205219.283543-1-geomatsi@gmail.com/#t
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
82 lines
2 KiB
C
82 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/sched.h>
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#include <asm/sbi.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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void flush_tlb_all(void)
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{
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sbi_remote_sfence_vma(NULL, 0, -1);
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}
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static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start,
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unsigned long size, unsigned long stride)
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{
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struct cpumask *pmask = &mm->context.tlb_stale_mask;
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struct cpumask *cmask = mm_cpumask(mm);
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unsigned int cpuid;
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bool broadcast;
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if (cpumask_empty(cmask))
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return;
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cpuid = get_cpu();
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/* check if the tlbflush needs to be sent to other CPUs */
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broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids;
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if (static_branch_unlikely(&use_asid_allocator)) {
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unsigned long asid = atomic_long_read(&mm->context.id);
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/*
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* TLB will be immediately flushed on harts concurrently
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* executing this MM context. TLB flush on other harts
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* is deferred until this MM context migrates there.
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*/
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cpumask_setall(pmask);
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cpumask_clear_cpu(cpuid, pmask);
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cpumask_andnot(pmask, pmask, cmask);
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if (broadcast) {
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sbi_remote_sfence_vma_asid(cmask, start, size, asid);
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} else if (size <= stride) {
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local_flush_tlb_page_asid(start, asid);
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} else {
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local_flush_tlb_all_asid(asid);
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}
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} else {
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if (broadcast) {
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sbi_remote_sfence_vma(cmask, start, size);
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} else if (size <= stride) {
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local_flush_tlb_page(start);
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} else {
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local_flush_tlb_all();
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}
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}
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put_cpu();
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}
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void flush_tlb_mm(struct mm_struct *mm)
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{
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__sbi_tlb_flush_range(mm, 0, -1, PAGE_SIZE);
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
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{
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__sbi_tlb_flush_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE);
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}
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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__sbi_tlb_flush_range(vma->vm_mm, start, end - start, PAGE_SIZE);
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}
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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__sbi_tlb_flush_range(vma->vm_mm, start, end - start, PMD_SIZE);
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}
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#endif
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