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01bf92788e
The UniPhier outer cache (arch/arm/mm/cache-uniphier.c) has 128 byte line length and its tags are also managed per 128 byte line. This is very unfortunate, but the current 64 byte alignment for kmalloc() causes sharing problems on DMA if used with this outer cache. This commit adds ARM_L1_CACHE_SHIFT_7 to increase the DMA minimum alignment to 128 byte if CACHE_UNIPHIER is enabled. There are several drivers that assume aligning to L1_CACHE_BYTES will be DMA safe, so this commit also changes the L1_CACHE_BYTES for safety. Having said that, I hesitate to align all the other SoCs in Multi platform to the UniPhier's requirement. So, I am disabling the CONFIG_CACHE_UNIPHIER by default, so that multi_v7_defconfig will still stay with CONFIG_ARM_L1_CACHE_SHIFT=6. With this commit, UniPhier SoCs will become slower, but it is much better than system crash. If desired, the outer-cache can be enabled by merge_config or something. Note: The UniPhier PH1-Pro5 SoC is equipped also with L3 cache with 256 byte line size but its tags are managed per 128 byte sub-line. So, ARM_L1_CACHE_SHIFT_7 should be fine for all the UniPhier SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
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