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41cd08560b
Create the dts files for each core and splits the devices between the two cores for P1020RDB. Core0 has core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb, eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi. Core1 has l2, eth0, crypto. MPIC is shared between two cores but each core will protect its interrupts from other core by using "protected-sources" of mpic. Fix compatible property for global-util node of P1020si.dtsi. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
377 lines
8.1 KiB
Text
377 lines
8.1 KiB
Text
/*
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* P1020si Device Tree Source
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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compatible = "fsl,P1020";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,P1020@0 {
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device_type = "cpu";
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reg = <0x0>;
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next-level-cache = <&L2>;
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};
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PowerPC,P1020@1 {
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device_type = "cpu";
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reg = <0x1>;
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next-level-cache = <&L2>;
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};
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};
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localbus@ffe05000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
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reg = <0 0xffe05000 0 0x1000>;
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interrupts = <19 2>;
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interrupt-parent = <&mpic>;
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};
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soc@ffe00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,p1020-immr", "simple-bus";
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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bus-frequency = <0>; // Filled out by uboot.
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <12>;
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};
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ecm@1000 {
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compatible = "fsl,p1020-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <16 2>;
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interrupt-parent = <&mpic>;
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};
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memory-controller@2000 {
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compatible = "fsl,p1020-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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spi@7000 {
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cell-index = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,espi";
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reg = <0x7000 0x1000>;
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interrupts = <59 0x2>;
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interrupt-parent = <&mpic>;
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mode = "cpu";
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};
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gpio: gpio-controller@f000 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8572-gpio";
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reg = <0xf000 0x100>;
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interrupts = <47 0x2>;
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interrupt-parent = <&mpic>;
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gpio-controller;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,p1020-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x40000>; // L2,256K
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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mdio@24000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,etsec2-mdio";
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reg = <0x24000 0x1000 0xb0030 0x4>;
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};
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mdio@25000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,etsec2-tbi";
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reg = <0x25000 0x1000 0xb1030 0x4>;
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};
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enet0: ethernet@b0000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "fsl,etsec2";
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fsl,num_rx_queues = <0x8>;
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fsl,num_tx_queues = <0x8>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupt-parent = <&mpic>;
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queue-group@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xb0000 0x1000>;
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interrupts = <29 2 30 2 34 2>;
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};
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queue-group@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xb4000 0x1000>;
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interrupts = <17 2 18 2 24 2>;
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};
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};
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enet1: ethernet@b1000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "fsl,etsec2";
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fsl,num_rx_queues = <0x8>;
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fsl,num_tx_queues = <0x8>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupt-parent = <&mpic>;
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queue-group@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xb1000 0x1000>;
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interrupts = <35 2 36 2 40 2>;
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};
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queue-group@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xb5000 0x1000>;
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interrupts = <51 2 52 2 67 2>;
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};
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};
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enet2: ethernet@b2000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "fsl,etsec2";
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fsl,num_rx_queues = <0x8>;
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fsl,num_tx_queues = <0x8>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupt-parent = <&mpic>;
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queue-group@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xb2000 0x1000>;
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interrupts = <31 2 32 2 33 2>;
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};
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queue-group@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xb6000 0x1000>;
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interrupts = <25 2 26 2 27 2>;
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};
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};
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usb@22000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl-usb2-dr";
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reg = <0x22000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <28 0x2>;
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};
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/* USB2 is shared with localbus, so it must be disabled
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by default. We can't put 'status = "disabled";' here
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since U-Boot doesn't clear the status property when
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it enables USB2. OTOH, U-Boot does create a new node
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when there isn't any. So, just comment it out.
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usb@23000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl-usb2-dr";
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reg = <0x23000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <46 0x2>;
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phy_type = "ulpi";
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};
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*/
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sdhci@2e000 {
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compatible = "fsl,p1020-esdhc", "fsl,esdhc";
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reg = <0x2e000 0x1000>;
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interrupts = <72 0x2>;
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interrupt-parent = <&mpic>;
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/* Filled in by U-Boot */
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clock-frequency = <0>;
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};
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crypto@30000 {
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compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
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"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <45 2 58 2>;
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interrupt-parent = <&mpic>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0xbfe>;
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fsl,descriptor-types-mask = <0x3ab0ebf>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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msi@41600 {
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compatible = "fsl,p1020-msi", "fsl,mpic-msi";
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reg = <0x41600 0x80>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe0 0
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0xe1 0
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0xe2 0
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0xe3 0
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0xe4 0
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0xe5 0
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0xe6 0
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0xe7 0>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 { //global utilities block
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compatible = "fsl,p1020-guts","fsl,p2020-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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};
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pci0: pcie@ffe09000 {
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0 0xffe09000 0 0x1000>;
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bus-range = <0 255>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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pci1: pcie@ffe0a000 {
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0 0xffe0a000 0 0x1000>;
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bus-range = <0 255>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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};
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