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![John Bonesio](/assets/img/avatar_default.png)
This patch creates mpc5200b.dtsi containing the information for the MPC5200b SoC then modifies all of the dts files for MPC5200b based systems to use mpc5200b.dtsi. Signed-off-by: John Bonesio <bones@secretlab.ca> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
137 lines
3.1 KiB
Text
137 lines
3.1 KiB
Text
/*
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* phyCORE-MPC5200B-tiny (pcm030) board Device Tree Source
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*
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* Copyright 2006 Pengutronix
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* Sascha Hauer <s.hauer@pengutronix.de>
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* Copyright 2007 Pengutronix
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* Juergen Beisert <j.beisert@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "mpc5200b.dtsi"
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/ {
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model = "phytec,pcm030";
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compatible = "phytec,pcm030";
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soc5200@f0000000 {
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timer@600 { // General Purpose Timer
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fsl,has-wdt;
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};
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gpt2: timer@620 { // General Purpose Timer in GPIO mode
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compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt3: timer@630 { // General Purpose Timer in GPIO mode
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compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt4: timer@640 { // General Purpose Timer in GPIO mode
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compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt5: timer@650 { // General Purpose Timer in GPIO mode
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compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt6: timer@660 { // General Purpose Timer in GPIO mode
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compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt7: timer@670 { // General Purpose Timer in GPIO mode
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compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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};
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psc@2000 { /* PSC1 in ac97 mode */
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compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
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cell-index = <0>;
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};
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/* PSC2 port is used by CAN1/2 */
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psc@2200 {
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status = "disabled";
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};
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psc@2400 { /* PSC3 in UART mode */
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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};
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/* PSC4 is ??? */
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psc@2600 {
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status = "disabled";
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};
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/* PSC5 is ??? */
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psc@2800 {
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status = "disabled";
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};
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psc@2c00 { /* PSC6 in UART mode */
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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};
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ethernet@3000 {
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phy-handle = <&phy0>;
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};
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mdio@3000 {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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i2c@3d40 {
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rtc@51 {
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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};
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eeprom@52 {
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compatible = "catalyst,24c32";
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reg = <0x52>;
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pagesize = <32>;
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};
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};
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sram@8000 {
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compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
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reg = <0x8000 0x4000>;
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};
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};
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pci@f0000d00 {
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
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0xc000 0 0 2 &mpc5200_pic 1 1 3
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0xc000 0 0 3 &mpc5200_pic 1 2 3
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0xc000 0 0 4 &mpc5200_pic 1 3 3
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0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
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0xc800 0 0 2 &mpc5200_pic 1 2 3
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0xc800 0 0 3 &mpc5200_pic 1 3 3
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0xc800 0 0 4 &mpc5200_pic 0 0 3>;
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ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
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0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
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0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
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};
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localbus {
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status = "disabled";
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};
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};
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