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![Linus Torvalds](/assets/img/avatar_default.png)
* 'next/cross-platform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: ARM: Consolidate the clkdev header files ARM: set vga memory base at run-time ARM: convert PCI defines to variables ARM: pci: make pcibios_assign_all_busses use pci_has_flag ARM: remove unnecessary mach/hardware.h includes pci: move microblaze and powerpc pci flag functions into asm-generic powerpc: rename ppc_pci_*_flags to pci_*_flags Fix up conflicts in arch/microblaze/include/asm/pci-bridge.h
714 lines
18 KiB
C
714 lines
18 KiB
C
/*
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* MPC83xx/85xx/86xx PCI/PCIE support routing.
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*
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* Copyright 2007-2011 Freescale Semiconductor, Inc.
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* Copyright 2008-2009 MontaVista Software, Inc.
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*
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* Initial author: Xianghua Xiao <x.xiao@freescale.com>
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* Recode: ZHANG WEI <wei.zhang@freescale.com>
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* Rewrite the routing for Frescale PCI and PCI Express
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* Roy Zang <tie-fei.zang@freescale.com>
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* MPC83xx PCI-Express support:
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* Tony Li <tony.li@freescale.com>
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/memblock.h>
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#include <linux/log2.h>
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#include <linux/slab.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
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static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
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{
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u8 progif;
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/* if we aren't a PCIe don't bother */
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if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
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return;
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/* if we aren't in host mode don't bother */
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pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
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if (progif & 0x1)
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return;
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dev->class = PCI_CLASS_BRIDGE_PCI << 8;
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fsl_pcie_bus_fixup = 1;
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return;
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}
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static int __init fsl_pcie_check_link(struct pci_controller *hose)
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{
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u32 val;
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early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
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if (val < PCIE_LTSSM_L0)
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return 1;
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return 0;
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}
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#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
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static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
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unsigned int index, const struct resource *res,
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resource_size_t offset)
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{
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resource_size_t pci_addr = res->start - offset;
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resource_size_t phys_addr = res->start;
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resource_size_t size = resource_size(res);
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u32 flags = 0x80044000; /* enable & mem R/W */
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unsigned int i;
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pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
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(u64)res->start, (u64)size);
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if (res->flags & IORESOURCE_PREFETCH)
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flags |= 0x10000000; /* enable relaxed ordering */
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for (i = 0; size > 0; i++) {
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unsigned int bits = min(__ilog2(size),
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__ffs(pci_addr | phys_addr));
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if (index + i >= 5)
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return -1;
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out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
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out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
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out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
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out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
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pci_addr += (resource_size_t)1U << bits;
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phys_addr += (resource_size_t)1U << bits;
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size -= (resource_size_t)1U << bits;
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}
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return i;
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}
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/* atmu setup for fsl pci/pcie controller */
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static void __init setup_pci_atmu(struct pci_controller *hose,
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struct resource *rsrc)
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{
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struct ccsr_pci __iomem *pci;
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int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
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u64 mem, sz, paddr_hi = 0;
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u64 paddr_lo = ULLONG_MAX;
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u32 pcicsrbar = 0, pcicsrbar_sz;
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u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
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PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
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char *name = hose->dn->full_name;
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pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
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(u64)rsrc->start, (u64)resource_size(rsrc));
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if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) {
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win_idx = 2;
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start_idx = 0;
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end_idx = 3;
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}
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pci = ioremap(rsrc->start, resource_size(rsrc));
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if (!pci) {
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dev_err(hose->parent, "Unable to map ATMU registers\n");
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return;
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}
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/* Disable all windows (except powar0 since it's ignored) */
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for(i = 1; i < 5; i++)
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out_be32(&pci->pow[i].powar, 0);
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for (i = start_idx; i < end_idx; i++)
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out_be32(&pci->piw[i].piwar, 0);
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/* Setup outbound MEM window */
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for(i = 0, j = 1; i < 3; i++) {
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if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
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continue;
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paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
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paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
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n = setup_one_atmu(pci, j, &hose->mem_resources[i],
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hose->pci_mem_offset);
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if (n < 0 || j >= 5) {
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pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
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hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
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} else
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j += n;
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}
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/* Setup outbound IO window */
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if (hose->io_resource.flags & IORESOURCE_IO) {
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if (j >= 5) {
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pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
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} else {
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pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
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"phy base 0x%016llx.\n",
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(u64)hose->io_resource.start,
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(u64)resource_size(&hose->io_resource),
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(u64)hose->io_base_phys);
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out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
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out_be32(&pci->pow[j].potear, 0);
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out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
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/* Enable, IO R/W */
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out_be32(&pci->pow[j].powar, 0x80088000
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| (__ilog2(hose->io_resource.end
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- hose->io_resource.start + 1) - 1));
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}
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}
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/* convert to pci address space */
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paddr_hi -= hose->pci_mem_offset;
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paddr_lo -= hose->pci_mem_offset;
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if (paddr_hi == paddr_lo) {
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pr_err("%s: No outbound window space\n", name);
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return ;
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}
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if (paddr_lo == 0) {
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pr_err("%s: No space for inbound window\n", name);
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return ;
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}
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/* setup PCSRBAR/PEXCSRBAR */
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early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
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early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
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pcicsrbar_sz = ~pcicsrbar_sz + 1;
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if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
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(paddr_lo > 0x100000000ull))
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pcicsrbar = 0x100000000ull - pcicsrbar_sz;
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else
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pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
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early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
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paddr_lo = min(paddr_lo, (u64)pcicsrbar);
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pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
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/* Setup inbound mem window */
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mem = memblock_end_of_DRAM();
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sz = min(mem, paddr_lo);
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mem_log = __ilog2_u64(sz);
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/* PCIe can overmap inbound & outbound since RX & TX are separated */
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if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
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/* Size window to exact size if power-of-two or one size up */
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if ((1ull << mem_log) != mem) {
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if ((1ull << mem_log) > mem)
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pr_info("%s: Setting PCI inbound window "
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"greater than memory size\n", name);
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mem_log++;
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}
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piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
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/* Setup inbound memory window */
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out_be32(&pci->piw[win_idx].pitar, 0x00000000);
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out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
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out_be32(&pci->piw[win_idx].piwar, piwar);
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win_idx--;
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hose->dma_window_base_cur = 0x00000000;
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hose->dma_window_size = (resource_size_t)sz;
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} else {
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u64 paddr = 0;
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/* Setup inbound memory window */
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out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
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out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
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out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
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win_idx--;
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paddr += 1ull << mem_log;
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sz -= 1ull << mem_log;
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if (sz) {
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mem_log = __ilog2_u64(sz);
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piwar |= (mem_log - 1);
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out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
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out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
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out_be32(&pci->piw[win_idx].piwar, piwar);
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win_idx--;
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paddr += 1ull << mem_log;
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}
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hose->dma_window_base_cur = 0x00000000;
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hose->dma_window_size = (resource_size_t)paddr;
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}
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if (hose->dma_window_size < mem) {
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#ifndef CONFIG_SWIOTLB
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pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
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"map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
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name);
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#endif
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/* adjusting outbound windows could reclaim space in mem map */
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if (paddr_hi < 0xffffffffull)
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pr_warning("%s: WARNING: Outbound window cfg leaves "
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"gaps in memory map. Adjusting the memory map "
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"could reduce unnecessary bounce buffering.\n",
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name);
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pr_info("%s: DMA window size is 0x%llx\n", name,
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(u64)hose->dma_window_size);
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}
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iounmap(pci);
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}
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static void __init setup_pci_cmd(struct pci_controller *hose)
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{
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u16 cmd;
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int cap_x;
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early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
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| PCI_COMMAND_IO;
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early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
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cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
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if (cap_x) {
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int pci_x_cmd = cap_x + PCI_X_CMD;
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cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
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| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
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early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
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} else {
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early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
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}
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}
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void fsl_pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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int i;
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if ((bus->parent == hose->bus) &&
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((fsl_pcie_bus_fixup &&
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early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
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(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
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{
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for (i = 0; i < 4; ++i) {
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struct resource *res = bus->resource[i];
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struct resource *par = bus->parent->resource[i];
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if (res) {
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res->start = 0;
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res->end = 0;
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res->flags = 0;
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}
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if (res && par) {
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res->start = par->start;
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res->end = par->end;
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res->flags = par->flags;
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}
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}
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}
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}
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int __init fsl_add_bridge(struct device_node *dev, int is_primary)
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{
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int len;
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struct pci_controller *hose;
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struct resource rsrc;
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const int *bus_range;
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u8 progif;
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if (!of_device_is_available(dev)) {
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pr_warning("%s: disabled\n", dev->full_name);
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return -ENODEV;
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}
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pr_debug("Adding PCI host bridge %s\n", dev->full_name);
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/* Fetch host bridge registers address */
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if (of_address_to_resource(dev, 0, &rsrc)) {
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printk(KERN_WARNING "Can't get pci register base!");
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return -ENOMEM;
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}
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/* Get bus range if any */
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bus_range = of_get_property(dev, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int))
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printk(KERN_WARNING "Can't get bus-range for %s, assume"
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" bus 0\n", dev->full_name);
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pci_add_flags(PCI_REASSIGN_ALL_BUS);
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hose = pcibios_alloc_controller(dev);
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if (!hose)
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return -ENOMEM;
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hose->first_busno = bus_range ? bus_range[0] : 0x0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
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PPC_INDIRECT_TYPE_BIG_ENDIAN);
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early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
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if ((progif & 1) == 1) {
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/* unmap cfg_data & cfg_addr separately if not on same page */
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if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
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((unsigned long)hose->cfg_addr & PAGE_MASK))
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iounmap(hose->cfg_data);
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iounmap(hose->cfg_addr);
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pcibios_free_controller(hose);
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return 0;
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}
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setup_pci_cmd(hose);
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/* check PCI express link status */
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if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
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hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
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PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
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if (fsl_pcie_check_link(hose))
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hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
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}
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printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
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"Firmware bus number: %d->%d\n",
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(unsigned long long)rsrc.start, hose->first_busno,
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hose->last_busno);
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pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
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hose, hose->cfg_addr, hose->cfg_data);
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/* Interpret the "ranges" property */
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/* This also maps the I/O region and sets isa_io/mem_base */
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pci_process_bridge_OF_ranges(hose, dev, is_primary);
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/* Setup PEX window registers */
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setup_pci_atmu(hose, &rsrc);
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return 0;
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}
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#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
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#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
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struct mpc83xx_pcie_priv {
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void __iomem *cfg_type0;
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void __iomem *cfg_type1;
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u32 dev_base;
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};
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struct pex_inbound_window {
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u32 ar;
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u32 tar;
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u32 barl;
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u32 barh;
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};
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/*
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* With the convention of u-boot, the PCIE outbound window 0 serves
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* as configuration transactions outbound.
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*/
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#define PEX_OUTWIN0_BAR 0xCA4
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#define PEX_OUTWIN0_TAL 0xCA8
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#define PEX_OUTWIN0_TAH 0xCAC
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#define PEX_RC_INWIN_BASE 0xE60
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#define PEX_RCIWARn_EN 0x1
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static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* Workaround for the HW bug: for Type 0 configure transactions the
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* PCI-E controller does not check the device number bits and just
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* assumes that the device number bits are 0.
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*/
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if (bus->number == hose->first_busno ||
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bus->primary == hose->first_busno) {
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if (devfn & 0xf8)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
}
|
|
|
|
if (ppc_md.pci_exclude_device) {
|
|
if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
}
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
|
|
unsigned int devfn, int offset)
|
|
{
|
|
struct pci_controller *hose = pci_bus_to_host(bus);
|
|
struct mpc83xx_pcie_priv *pcie = hose->dn->data;
|
|
u32 dev_base = bus->number << 24 | devfn << 16;
|
|
int ret;
|
|
|
|
ret = mpc83xx_pcie_exclude_device(bus, devfn);
|
|
if (ret)
|
|
return NULL;
|
|
|
|
offset &= 0xfff;
|
|
|
|
/* Type 0 */
|
|
if (bus->number == hose->first_busno)
|
|
return pcie->cfg_type0 + offset;
|
|
|
|
if (pcie->dev_base == dev_base)
|
|
goto mapped;
|
|
|
|
out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
|
|
|
|
pcie->dev_base = dev_base;
|
|
mapped:
|
|
return pcie->cfg_type1 + offset;
|
|
}
|
|
|
|
static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
|
|
int offset, int len, u32 *val)
|
|
{
|
|
void __iomem *cfg_addr;
|
|
|
|
cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
|
|
if (!cfg_addr)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
switch (len) {
|
|
case 1:
|
|
*val = in_8(cfg_addr);
|
|
break;
|
|
case 2:
|
|
*val = in_le16(cfg_addr);
|
|
break;
|
|
default:
|
|
*val = in_le32(cfg_addr);
|
|
break;
|
|
}
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
|
|
int offset, int len, u32 val)
|
|
{
|
|
struct pci_controller *hose = pci_bus_to_host(bus);
|
|
void __iomem *cfg_addr;
|
|
|
|
cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
|
|
if (!cfg_addr)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
/* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
|
|
if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
|
|
val &= 0xffffff00;
|
|
|
|
switch (len) {
|
|
case 1:
|
|
out_8(cfg_addr, val);
|
|
break;
|
|
case 2:
|
|
out_le16(cfg_addr, val);
|
|
break;
|
|
default:
|
|
out_le32(cfg_addr, val);
|
|
break;
|
|
}
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
static struct pci_ops mpc83xx_pcie_ops = {
|
|
.read = mpc83xx_pcie_read_config,
|
|
.write = mpc83xx_pcie_write_config,
|
|
};
|
|
|
|
static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
|
|
struct resource *reg)
|
|
{
|
|
struct mpc83xx_pcie_priv *pcie;
|
|
u32 cfg_bar;
|
|
int ret = -ENOMEM;
|
|
|
|
pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
|
|
if (!pcie)
|
|
return ret;
|
|
|
|
pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
|
|
if (!pcie->cfg_type0)
|
|
goto err0;
|
|
|
|
cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
|
|
if (!cfg_bar) {
|
|
/* PCI-E isn't configured. */
|
|
ret = -ENODEV;
|
|
goto err1;
|
|
}
|
|
|
|
pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
|
|
if (!pcie->cfg_type1)
|
|
goto err1;
|
|
|
|
WARN_ON(hose->dn->data);
|
|
hose->dn->data = pcie;
|
|
hose->ops = &mpc83xx_pcie_ops;
|
|
|
|
out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
|
|
out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
|
|
|
|
if (fsl_pcie_check_link(hose))
|
|
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
|
|
|
|
return 0;
|
|
err1:
|
|
iounmap(pcie->cfg_type0);
|
|
err0:
|
|
kfree(pcie);
|
|
return ret;
|
|
|
|
}
|
|
|
|
int __init mpc83xx_add_bridge(struct device_node *dev)
|
|
{
|
|
int ret;
|
|
int len;
|
|
struct pci_controller *hose;
|
|
struct resource rsrc_reg;
|
|
struct resource rsrc_cfg;
|
|
const int *bus_range;
|
|
int primary;
|
|
|
|
is_mpc83xx_pci = 1;
|
|
|
|
if (!of_device_is_available(dev)) {
|
|
pr_warning("%s: disabled by the firmware.\n",
|
|
dev->full_name);
|
|
return -ENODEV;
|
|
}
|
|
pr_debug("Adding PCI host bridge %s\n", dev->full_name);
|
|
|
|
/* Fetch host bridge registers address */
|
|
if (of_address_to_resource(dev, 0, &rsrc_reg)) {
|
|
printk(KERN_WARNING "Can't get pci register base!\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
|
|
|
|
if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
|
|
printk(KERN_WARNING
|
|
"No pci config register base in dev tree, "
|
|
"using default\n");
|
|
/*
|
|
* MPC83xx supports up to two host controllers
|
|
* one at 0x8500 has config space registers at 0x8300
|
|
* one at 0x8600 has config space registers at 0x8380
|
|
*/
|
|
if ((rsrc_reg.start & 0xfffff) == 0x8500)
|
|
rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
|
|
else if ((rsrc_reg.start & 0xfffff) == 0x8600)
|
|
rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
|
|
}
|
|
/*
|
|
* Controller at offset 0x8500 is primary
|
|
*/
|
|
if ((rsrc_reg.start & 0xfffff) == 0x8500)
|
|
primary = 1;
|
|
else
|
|
primary = 0;
|
|
|
|
/* Get bus range if any */
|
|
bus_range = of_get_property(dev, "bus-range", &len);
|
|
if (bus_range == NULL || len < 2 * sizeof(int)) {
|
|
printk(KERN_WARNING "Can't get bus-range for %s, assume"
|
|
" bus 0\n", dev->full_name);
|
|
}
|
|
|
|
pci_add_flags(PCI_REASSIGN_ALL_BUS);
|
|
hose = pcibios_alloc_controller(dev);
|
|
if (!hose)
|
|
return -ENOMEM;
|
|
|
|
hose->first_busno = bus_range ? bus_range[0] : 0;
|
|
hose->last_busno = bus_range ? bus_range[1] : 0xff;
|
|
|
|
if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
|
|
ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
|
|
if (ret)
|
|
goto err0;
|
|
} else {
|
|
setup_indirect_pci(hose, rsrc_cfg.start,
|
|
rsrc_cfg.start + 4, 0);
|
|
}
|
|
|
|
printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
|
|
"Firmware bus number: %d->%d\n",
|
|
(unsigned long long)rsrc_reg.start, hose->first_busno,
|
|
hose->last_busno);
|
|
|
|
pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
|
|
hose, hose->cfg_addr, hose->cfg_data);
|
|
|
|
/* Interpret the "ranges" property */
|
|
/* This also maps the I/O region and sets isa_io/mem_base */
|
|
pci_process_bridge_OF_ranges(hose, dev, primary);
|
|
|
|
return 0;
|
|
err0:
|
|
pcibios_free_controller(hose);
|
|
return ret;
|
|
}
|
|
#endif /* CONFIG_PPC_83xx */
|
|
|
|
u64 fsl_pci_immrbar_base(struct pci_controller *hose)
|
|
{
|
|
#ifdef CONFIG_PPC_83xx
|
|
if (is_mpc83xx_pci) {
|
|
struct mpc83xx_pcie_priv *pcie = hose->dn->data;
|
|
struct pex_inbound_window *in;
|
|
int i;
|
|
|
|
/* Walk the Root Complex Inbound windows to match IMMR base */
|
|
in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
|
|
for (i = 0; i < 4; i++) {
|
|
/* not enabled, skip */
|
|
if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
|
|
continue;
|
|
|
|
if (get_immrbase() == in_le32(&in[i].tar))
|
|
return (u64)in_le32(&in[i].barh) << 32 |
|
|
in_le32(&in[i].barl);
|
|
}
|
|
|
|
printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
|
|
if (!is_mpc83xx_pci) {
|
|
u32 base;
|
|
|
|
pci_bus_read_config_dword(hose->bus,
|
|
PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
|
|
return base;
|
|
}
|
|
#endif
|
|
|
|
return 0;
|
|
}
|