Yicong Yang 0242737dc4 perf/smmuv3: Enable HiSilicon Erratum 162001900 quirk for HIP08/09 ... Some HiSilicon SMMU PMCG suffers the erratum 162001900 that the PMU disable control sometimes fail to disable the counters. This will lead to error or inaccurate data since before we enable the counters the counter's still counting for the event used in last perf session. This patch tries to fix this by hardening the global disable process. Before disable the PMU, writing an invalid event type (0xffff) to focibly stop the counters. Correspondingly restore each events on pmu::pmu_enable(). Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Link: https://lore.kernel.org/r/20230814124012.58013-1-yangyicong@huawei.com Signed-off-by: Will Deacon <will@kernel.org>		2023-08-15 12:50:53 +01:00
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arc
arm	arm: docs: Move Arm documentation to Documentation/arch/	2023-06-12 06:33:40 -06:00
arm64	perf/smmuv3: Enable HiSilicon Erratum 162001900 quirk for HIP08/09	2023-08-15 12:50:53 +01:00
ia64
m68k
nios2
openrisc
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sparc
x86	Documentation/x86: Documentation for MON group move feature	2023-06-07 12:42:12 +02:00
xtensa
index.rst	docs: arm64: Move arm64 documentation under Documentation/arch/	2023-06-21 08:51:51 -06:00