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cb823ed991
Having taken the first step in encapsulating the functionality by moving the related files under gt/, the next step is to start encapsulating by passing around the relevant structs rather than the global drm_i915_private. In this step, we pass intel_gt to intel_reset.c Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190712192953.9187-1-chris@chris-wilson.co.uk
51 lines
1.1 KiB
C
51 lines
1.1 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2018 Intel Corporation
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*/
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#include "igt_reset.h"
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#include "gt/intel_engine.h"
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#include "gt/intel_gt.h"
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#include "../i915_drv.h"
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void igt_global_reset_lock(struct intel_gt *gt)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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pr_debug("%s: current gpu_error=%08lx\n", __func__, gt->reset.flags);
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while (test_and_set_bit(I915_RESET_BACKOFF, >->reset.flags))
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wait_event(gt->reset.queue,
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!test_bit(I915_RESET_BACKOFF, >->reset.flags));
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for_each_engine(engine, gt->i915, id) {
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while (test_and_set_bit(I915_RESET_ENGINE + id,
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>->reset.flags))
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wait_on_bit(>->reset.flags, I915_RESET_ENGINE + id,
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TASK_UNINTERRUPTIBLE);
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}
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}
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void igt_global_reset_unlock(struct intel_gt *gt)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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for_each_engine(engine, gt->i915, id)
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clear_bit(I915_RESET_ENGINE + id, >->reset.flags);
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clear_bit(I915_RESET_BACKOFF, >->reset.flags);
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wake_up_all(>->reset.queue);
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}
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bool igt_force_reset(struct intel_gt *gt)
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{
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intel_gt_set_wedged(gt);
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intel_gt_reset(gt, 0, NULL);
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return !intel_gt_is_wedged(gt);
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}
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