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230f7ede6c
Extends FSL EHCI platform driver glue layer to support MPC5121 USB controllers. MPC5121 Rev 2.0 silicon EHCI registers are in big endian format. The appropriate flags are set using the information in the platform data structure. MPC83xx system interface registers are not available on MPC512x, so the access to these registers is isolated in MPC512x case. Furthermore the USB controller clocks must be enabled before 512x register accesses which is done by providing platform specific init callback. The MPC512x internal USB PHY doesn't provide supply voltage. For boards using different power switches allow specifying DRVVBUS and PWR_FAULT signal polarity of the MPC5121 internal PHY using "fsl,invert-drvvbus" and "fsl,invert-pwr-fault" properties in the device tree USB nodes. Adds documentation for this new device tree bindings. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
48 lines
1.8 KiB
C
48 lines
1.8 KiB
C
/* Copyright (C) 2005-2010 Freescale Semiconductor, Inc.
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* Copyright (c) 2005 MontaVista Software
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _EHCI_FSL_H
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#define _EHCI_FSL_H
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/* offsets for the non-ehci registers in the FSL SOC USB controller */
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#define FSL_SOC_USB_ID 0x0
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#define ID_MSK 0x3f
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#define NID_MSK 0x3f00
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#define FSL_SOC_USB_ULPIVP 0x170
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#define FSL_SOC_USB_PORTSC1 0x184
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#define PORT_PTS_MSK (3<<30)
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#define PORT_PTS_UTMI (0<<30)
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#define PORT_PTS_ULPI (2<<30)
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#define PORT_PTS_SERIAL (3<<30)
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#define PORT_PTS_PTW (1<<28)
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#define FSL_SOC_USB_PORTSC2 0x188
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#define FSL_SOC_USB_USBGENCTRL 0x200
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#define USBGENCTRL_PPP (1 << 3)
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#define USBGENCTRL_PFP (1 << 2)
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#define FSL_SOC_USB_ISIPHYCTRL 0x204
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#define ISIPHYCTRL_PXE (1)
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#define ISIPHYCTRL_PHYE (1 << 4)
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#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
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#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
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#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
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#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
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#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
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#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
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#define SNOOP_SIZE_2GB 0x1e
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#endif /* _EHCI_FSL_H */
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