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![Chris Zankel](/assets/img/avatar_default.png)
The Xtensa port contained many header files that were never needed. This rather lengthy patch removes all those files. Unfortunately, there were many dependencies that needed to be updated, so this patch touches quite a few source files. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
202 lines
5.2 KiB
C
202 lines
5.2 KiB
C
/*
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* include/asm-xtensa/tlbflush.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_TLBFLUSH_H
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#define _XTENSA_TLBFLUSH_H
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#ifdef __KERNEL__
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#include <linux/stringify.h>
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#include <asm/processor.h>
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#define DTLB_WAY_PGD 7
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#define ITLB_ARF_WAYS 4
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#define DTLB_ARF_WAYS 4
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#define ITLB_HIT_BIT 3
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#define DTLB_HIT_BIT 4
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#ifndef __ASSEMBLY__
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/* TLB flushing:
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*
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* - flush_tlb_all() flushes all processes TLB entries
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* - flush_tlb_mm(mm) flushes the specified mm context TLB entries
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* - flush_tlb_page(mm, vmaddr) flushes a single page
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* - flush_tlb_range(mm, start, end) flushes a range of pages
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*/
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extern void flush_tlb_all(void);
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extern void flush_tlb_mm(struct mm_struct*);
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extern void flush_tlb_page(struct vm_area_struct*,unsigned long);
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extern void flush_tlb_range(struct vm_area_struct*,unsigned long,unsigned long);
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#define flush_tlb_kernel_range(start,end) flush_tlb_all()
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/* This is calld in munmap when we have freed up some page-table pages.
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* We don't need to do anything here, there's nothing special about our
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* page-table pages.
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*/
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static inline void flush_tlb_pgtables(struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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}
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/* TLB operations. */
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static inline unsigned long itlb_probe(unsigned long addr)
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{
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unsigned long tmp;
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__asm__ __volatile__("pitlb %0, %1\n\t" : "=a" (tmp) : "a" (addr));
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return tmp;
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}
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static inline unsigned long dtlb_probe(unsigned long addr)
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{
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unsigned long tmp;
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__asm__ __volatile__("pdtlb %0, %1\n\t" : "=a" (tmp) : "a" (addr));
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return tmp;
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}
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static inline void invalidate_itlb_entry (unsigned long probe)
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{
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__asm__ __volatile__("iitlb %0; isync\n\t" : : "a" (probe));
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}
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static inline void invalidate_dtlb_entry (unsigned long probe)
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{
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__asm__ __volatile__("idtlb %0; dsync\n\t" : : "a" (probe));
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}
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/* Use the .._no_isync functions with caution. Generally, these are
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* handy for bulk invalidates followed by a single 'isync'. The
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* caller must follow up with an 'isync', which can be relatively
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* expensive on some Xtensa implementations.
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*/
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static inline void invalidate_itlb_entry_no_isync (unsigned entry)
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{
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/* Caller must follow up with 'isync'. */
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__asm__ __volatile__ ("iitlb %0\n" : : "a" (entry) );
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}
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static inline void invalidate_dtlb_entry_no_isync (unsigned entry)
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{
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/* Caller must follow up with 'isync'. */
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__asm__ __volatile__ ("idtlb %0\n" : : "a" (entry) );
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}
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static inline void set_itlbcfg_register (unsigned long val)
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{
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__asm__ __volatile__("wsr %0, "__stringify(ITLBCFG)"\n\t" "isync\n\t"
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: : "a" (val));
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}
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static inline void set_dtlbcfg_register (unsigned long val)
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{
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__asm__ __volatile__("wsr %0, "__stringify(DTLBCFG)"; dsync\n\t"
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: : "a" (val));
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}
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static inline void set_ptevaddr_register (unsigned long val)
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{
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__asm__ __volatile__(" wsr %0, "__stringify(PTEVADDR)"; isync\n"
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: : "a" (val));
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}
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static inline unsigned long read_ptevaddr_register (void)
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{
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unsigned long tmp;
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__asm__ __volatile__("rsr %0, "__stringify(PTEVADDR)"\n\t" : "=a" (tmp));
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return tmp;
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}
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static inline void write_dtlb_entry (pte_t entry, int way)
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{
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__asm__ __volatile__("wdtlb %1, %0; dsync\n\t"
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: : "r" (way), "r" (entry) );
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}
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static inline void write_itlb_entry (pte_t entry, int way)
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{
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__asm__ __volatile__("witlb %1, %0; isync\n\t"
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: : "r" (way), "r" (entry) );
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}
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static inline void invalidate_page_directory (void)
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{
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invalidate_dtlb_entry (DTLB_WAY_PGD);
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invalidate_dtlb_entry (DTLB_WAY_PGD+1);
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invalidate_dtlb_entry (DTLB_WAY_PGD+2);
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}
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static inline void invalidate_itlb_mapping (unsigned address)
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{
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unsigned long tlb_entry;
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if (((tlb_entry = itlb_probe(address)) & (1 << ITLB_HIT_BIT)) != 0)
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invalidate_itlb_entry(tlb_entry);
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}
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static inline void invalidate_dtlb_mapping (unsigned address)
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{
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unsigned long tlb_entry;
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if (((tlb_entry = dtlb_probe(address)) & (1 << DTLB_HIT_BIT)) != 0)
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invalidate_dtlb_entry(tlb_entry);
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}
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#define check_pgt_cache() do { } while (0)
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/*
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* DO NOT USE THESE FUNCTIONS. These instructions aren't part of the Xtensa
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* ISA and exist only for test purposes..
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* You may find it helpful for MMU debugging, however.
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*
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* 'at' is the unmodified input register
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* 'as' is the output register, as follows (specific to the Linux config):
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*
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* as[31..12] contain the virtual address
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* as[11..08] are meaningless
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* as[07..00] contain the asid
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*/
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static inline unsigned long read_dtlb_virtual (int way)
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{
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unsigned long tmp;
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__asm__ __volatile__("rdtlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way));
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return tmp;
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}
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static inline unsigned long read_dtlb_translation (int way)
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{
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unsigned long tmp;
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__asm__ __volatile__("rdtlb1 %0, %1\n\t" : "=a" (tmp), "+a" (way));
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return tmp;
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}
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static inline unsigned long read_itlb_virtual (int way)
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{
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unsigned long tmp;
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__asm__ __volatile__("ritlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way));
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return tmp;
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}
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static inline unsigned long read_itlb_translation (int way)
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{
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unsigned long tmp;
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__asm__ __volatile__("ritlb1 %0, %1\n\t" : "=a" (tmp), "+a" (way));
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return tmp;
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _XTENSA_TLBFLUSH_H */
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