mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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eb785bef68
As usual, this is the largest branch, though this time a little under half of the total changes with 307 individual non-merge changesets. The largest changes are the addition of new machines, in particular the Tegra based Chromebook, the Renesas r8a7794 SoC, and DT support for the old i.MX1 platform. Other changes include - at91: various sam9 and sama5 updates - exynos: much extended Peach Pi/Pit (Chromebook 2) support - keystone: new peripherals - meson: added DT for meson6 SoC - mvebu: new device support for Armada 370/375 - qcom: improved support for IPQ8064 and MSM8x60 - rockchip: much improved support for rk3288 - shmobile: lots of updates all over the place - sunxi: dts license change - sunxi: more a23 device support - vexpress: CLCD DT description -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAVDWVG2CrR//JCVInAQJmARAAnU2I4VpJHlBeHC4CYr/GdRq0NqiFvQ38 7N/zevUI4l150DtejltbOX71JGM9vD3hq8VXZYBCEpTbG4el9PzAq28Fomtt4tmC PGbczQY8ZMvY1/MOT3XLZAd3TSUL0TZRt97t9bdLif6QyPafel5o2pd8D2OG7h+L Awtyk9LobT9jU3muFX3ZUfB3Gg2sNKphZjox9Le3gVjGd6g5teEqqMAehK2Y7ArJ kixrKck4vgduDdZe59o2yApAUsfIQv/joqu68jv3MUQrKmk4s543+rIdGDuLF5bz mEo7qtMXujoNaF3CyLYNEF2ZExIOJDdtmrwjHY8oKIFtIeI/faIJmeSChwa6794t Njj5bbnL0Pt61l4gUSFk2hUFo28gpiEB+Mm0R4E1hdoG15Iv6E+lpy44EmEmfz1c 9h0sATNGUrz18IrUk7jI1WwIaEJUwkbZ+8wKuWtvH+Z+mFA4ZlDykVcnVuELixpb vKmI3kcmEw2RsJjkYq3LcgXXQevE4mHRR1ow59yXTY6OR1LmVb7odKUwbrweofQO eytVb1deMeYXrBXT5/j6WmrlyDbYcuGsjO4WidT+zwYUiAMCE6bTpNwUWqumVEUv LjCBaN6BRIb89EBwt4xIvIu7ir9hNNRZnD8aa4afSzIYxknzZy73pjjT2+wu7jbU m15TwYyQG4E= =2Sq1 -----END PGP SIGNATURE----- Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Arnd Bergmann: "As usual, this is the largest branch, though this time a little under half of the total changes with 307 individual non-merge changesets. The largest changes are the addition of new machines, in particular the Tegra based Chromebook, the Renesas r8a7794 SoC, and DT support for the old i.MX1 platform. Other changes include - at91: various sam9 and sama5 updates - exynos: much extended Peach Pi/Pit (Chromebook 2) support - keystone: new peripherals - meson: added DT for meson6 SoC - mvebu: new device support for Armada 370/375 - qcom: improved support for IPQ8064 and MSM8x60 - rockchip: much improved support for rk3288 - shmobile: lots of updates all over the place - sunxi: dts license change - sunxi: more a23 device support - vexpress: CLCD DT description" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (308 commits) ARM: DTS: meson: update DTSI to add watchdog node ARM: dts: keystone-k2l: fix mdio io start address ARM: dts: keystone-k2e: fix mdio io start address ARM: dts: keystone-k2e: update usb1 node for dma properties ARM: dts: keystone: fix io range for usb_phy0 Revert "Merge tag 'hix5hd2-dt-for-3.18' of git://github.com/hisilicon/linux-hisi into next/dt" Revert "ARM: dts: hix5hd2: add wdg node" ARM: dts: add rk3288 i2s controller ARM: vexpress: Add CLCD Device Tree properties ARM: bcm2835: add I2S pinctrl to device tree ARM: meson: documentation: add bindings documentation ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS ARM: dts: mt6589: Change compatible string for GIC ARM: dts: mediatek: Add compatible property for aquaris5 ARM: dts: mt6589-aquaris5: Add boot argument earlyprintk ARM: dts: mt6589: Fix typo in GIC unit address ARM: dts: Build dtb for Mediatek board ARM: dts: keystone: fix bindings for pcie and usb clock nodes ARM: dts: keystone: k2l: Fix chip selects for SPI devices ARM: dts: keystone: add dsp gpio controllers nodes ...
524 lines
13 KiB
Text
524 lines
13 KiB
Text
/*
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* Device Tree Source for Renesas r8a7779
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Simon Horman
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/r8a7779-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "renesas,r8a7779";
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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clock-frequency = <1000000000>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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clock-frequency = <1000000000>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <2>;
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clock-frequency = <1000000000>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <3>;
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clock-frequency = <1000000000>;
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};
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};
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aliases {
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spi0 = &hspi0;
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spi1 = &hspi1;
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spi2 = &hspi2;
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};
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gic: interrupt-controller@f0001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xf0001000 0x1000>,
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<0xf0000100 0x100>;
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};
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gpio0: gpio@ffc40000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc40000 0x2c>;
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interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio1: gpio@ffc41000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc41000 0x2c>;
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interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio2: gpio@ffc42000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc42000 0x2c>;
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interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio3: gpio@ffc43000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc43000 0x2c>;
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interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio4: gpio@ffc44000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc44000 0x2c>;
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interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio5: gpio@ffc45000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc45000 0x2c>;
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interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio6: gpio@ffc46000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc46000 0x2c>;
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interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 9>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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irqpin0: irqpin@fe780010 {
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compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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status = "disabled";
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interrupt-controller;
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reg = <0xfe78001c 4>,
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<0xfe780010 4>,
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<0xfe780024 4>,
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<0xfe780044 4>,
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<0xfe780064 4>;
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interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
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0 28 IRQ_TYPE_LEVEL_HIGH
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0 29 IRQ_TYPE_LEVEL_HIGH
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0 30 IRQ_TYPE_LEVEL_HIGH>;
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sense-bitfield-width = <2>;
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};
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i2c0: i2c@ffc70000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc70000 0x1000>;
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interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
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status = "disabled";
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};
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i2c1: i2c@ffc71000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc71000 0x1000>;
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interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
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status = "disabled";
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};
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i2c2: i2c@ffc72000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc72000 0x1000>;
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interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
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status = "disabled";
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};
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i2c3: i2c@ffc73000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc73000 0x1000>;
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interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
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status = "disabled";
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};
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scif0: serial@ffe40000 {
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe40000 0x100>;
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interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif1: serial@ffe41000 {
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe41000 0x100>;
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interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif2: serial@ffe42000 {
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe42000 0x100>;
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interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif3: serial@ffe43000 {
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe43000 0x100>;
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interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif4: serial@ffe44000 {
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe44000 0x100>;
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interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif5: serial@ffe45000 {
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe45000 0x100>;
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interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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pfc: pfc@fffc0000 {
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compatible = "renesas,pfc-r8a7779";
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reg = <0xfffc0000 0x23c>;
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};
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thermal@ffc48000 {
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compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
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reg = <0xffc48000 0x38>;
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};
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tmu0: timer@ffd80000 {
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compatible = "renesas,tmu-r8a7779", "renesas,tmu";
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reg = <0xffd80000 0x30>;
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interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
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<0 33 IRQ_TYPE_LEVEL_HIGH>,
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<0 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
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clock-names = "fck";
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#renesas,channels = <3>;
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status = "disabled";
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};
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tmu1: timer@ffd81000 {
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compatible = "renesas,tmu-r8a7779", "renesas,tmu";
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reg = <0xffd81000 0x30>;
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interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
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<0 37 IRQ_TYPE_LEVEL_HIGH>,
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<0 38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
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clock-names = "fck";
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#renesas,channels = <3>;
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status = "disabled";
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};
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tmu2: timer@ffd82000 {
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compatible = "renesas,tmu-r8a7779", "renesas,tmu";
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reg = <0xffd82000 0x30>;
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interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
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<0 41 IRQ_TYPE_LEVEL_HIGH>,
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<0 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
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clock-names = "fck";
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#renesas,channels = <3>;
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status = "disabled";
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};
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sata: sata@fc600000 {
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compatible = "renesas,rcar-sata";
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reg = <0xfc600000 0x2000>;
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interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7779_CLK_SATA>;
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};
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sdhi0: sd@ffe4c000 {
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compatible = "renesas,sdhi-r8a7779";
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reg = <0xffe4c000 0x100>;
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interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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sdhi1: sd@ffe4d000 {
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compatible = "renesas,sdhi-r8a7779";
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reg = <0xffe4d000 0x100>;
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interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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sdhi2: sd@ffe4e000 {
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compatible = "renesas,sdhi-r8a7779";
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reg = <0xffe4e000 0x100>;
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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sdhi3: sd@ffe4f000 {
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compatible = "renesas,sdhi-r8a7779";
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reg = <0xffe4f000 0x100>;
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interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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hspi0: spi@fffc7000 {
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compatible = "renesas,hspi-r8a7779", "renesas,hspi";
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reg = <0xfffc7000 0x18>;
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interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
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status = "disabled";
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};
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hspi1: spi@fffc8000 {
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compatible = "renesas,hspi-r8a7779", "renesas,hspi";
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reg = <0xfffc8000 0x18>;
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interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
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status = "disabled";
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};
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hspi2: spi@fffc6000 {
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compatible = "renesas,hspi-r8a7779", "renesas,hspi";
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reg = <0xfffc6000 0x18>;
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interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
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status = "disabled";
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* External root clock */
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extal_clk: extal_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overriden by the board. */
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clock-frequency = <0>;
|
|
clock-output-names = "extal";
|
|
};
|
|
|
|
/* Special CPG clocks */
|
|
cpg_clocks: clocks@ffc80000 {
|
|
compatible = "renesas,r8a7779-cpg-clocks";
|
|
reg = <0xffc80000 0x30>;
|
|
clocks = <&extal_clk>;
|
|
#clock-cells = <1>;
|
|
clock-output-names = "plla", "z", "zs", "s",
|
|
"s1", "p", "b", "out";
|
|
};
|
|
|
|
/* Fixed factor clocks */
|
|
i_clk: i_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "i";
|
|
};
|
|
s3_clk: s3_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
|
|
#clock-cells = <0>;
|
|
clock-div = <8>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "s3";
|
|
};
|
|
s4_clk: s4_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
|
|
#clock-cells = <0>;
|
|
clock-div = <16>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "s4";
|
|
};
|
|
g_clk: g_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
|
|
#clock-cells = <0>;
|
|
clock-div = <24>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "g";
|
|
};
|
|
|
|
/* Gate clocks */
|
|
mstp0_clks: clocks@ffc80030 {
|
|
compatible = "renesas,r8a7779-mstp-clocks",
|
|
"renesas,cpg-mstp-clocks";
|
|
reg = <0xffc80030 4>;
|
|
clocks = <&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_S1>,
|
|
<&cpg_clocks R8A7779_CLK_S1>,
|
|
<&cpg_clocks R8A7779_CLK_S1>,
|
|
<&cpg_clocks R8A7779_CLK_S1>,
|
|
<&cpg_clocks R8A7779_CLK_S1>,
|
|
<&cpg_clocks R8A7779_CLK_S1>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7779_CLK_HSPI R8A7779_CLK_TMU2
|
|
R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
|
|
R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
|
|
R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
|
|
R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
|
|
R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
|
|
R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
|
|
R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
|
|
>;
|
|
clock-output-names =
|
|
"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
|
|
"hscif0", "scif5", "scif4", "scif3", "scif2",
|
|
"scif1", "scif0", "i2c3", "i2c2", "i2c1",
|
|
"i2c0";
|
|
};
|
|
mstp1_clks: clocks@ffc80034 {
|
|
compatible = "renesas,r8a7779-mstp-clocks",
|
|
"renesas,cpg-mstp-clocks";
|
|
reg = <0xffc80034 4>, <0xffc80044 4>;
|
|
clocks = <&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_S>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7779_CLK_USB01 R8A7779_CLK_USB2
|
|
R8A7779_CLK_DU R8A7779_CLK_VIN2
|
|
R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
|
|
R8A7779_CLK_ETHER R8A7779_CLK_SATA
|
|
R8A7779_CLK_PCIE R8A7779_CLK_VIN3
|
|
>;
|
|
clock-output-names =
|
|
"usb01", "usb2",
|
|
"du", "vin2",
|
|
"vin1", "vin0",
|
|
"ether", "sata",
|
|
"pcie", "vin3";
|
|
};
|
|
mstp3_clks: clocks@ffc8003c {
|
|
compatible = "renesas,r8a7779-mstp-clocks",
|
|
"renesas,cpg-mstp-clocks";
|
|
reg = <0xffc8003c 4>;
|
|
clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
|
|
<&s4_clk>, <&s4_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
|
|
R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
|
|
R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
|
|
>;
|
|
clock-output-names =
|
|
"sdhi3", "sdhi2", "sdhi1", "sdhi0",
|
|
"mmc1", "mmc0";
|
|
};
|
|
};
|
|
};
|