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204eaac625
and remove each ras IP's own debugfs creation this is required to fix ras when the driver does not use the drm load and unload callbacks due to ordering issues with the drm device node. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
83 lines
2.6 KiB
C
83 lines
2.6 KiB
C
/*
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* Copyright (C) 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "amdgpu.h"
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#include "amdgpu_ras.h"
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int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev)
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{
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int r;
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struct ras_ih_if ih_info = {
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.cb = NULL,
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};
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struct ras_fs_if fs_info = {
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.sysfs_name = "pcie_bif_err_count",
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};
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if (!adev->nbio.ras_if) {
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adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
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if (!adev->nbio.ras_if)
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return -ENOMEM;
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adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;
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adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
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adev->nbio.ras_if->sub_block_index = 0;
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strcpy(adev->nbio.ras_if->name, "pcie_bif");
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}
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ih_info.head = fs_info.head = *adev->nbio.ras_if;
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r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,
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&fs_info, &ih_info);
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if (r)
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goto free;
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if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
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r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
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if (r)
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goto late_fini;
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r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
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if (r)
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goto late_fini;
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} else {
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r = 0;
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goto free;
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}
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return 0;
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late_fini:
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amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info);
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free:
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kfree(adev->nbio.ras_if);
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adev->nbio.ras_if = NULL;
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return r;
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}
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void amdgpu_nbio_ras_fini(struct amdgpu_device *adev)
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{
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if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF) &&
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adev->nbio.ras_if) {
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struct ras_common_if *ras_if = adev->nbio.ras_if;
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struct ras_ih_if ih_info = {
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.cb = NULL,
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};
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amdgpu_ras_late_fini(adev, ras_if, &ih_info);
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kfree(ras_if);
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}
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}
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