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b4a7db71ea
Non-outbound data metrics are non useful so mark them as legacy. Bucket new perf counters into device and not device ip. Bind events to chip instead of IP. Report available event counters and not number of hw counter banks. Move DF public macros to private since not needed outside of IP version. v5: cleanup by moving per chip configs into structs v4: After more discussion, replace *_LEGACY references with IP references to indicate concept of pmu-typed versus event-config-typed event registration. v3: attr groups const array is global but attr groups are allocated per device which doesn't work and causes problems on memory allocation and de-allocation for pmu unregister. Switch to building const attr groups per pmu instead to simplify solution. v2: add comments on sysfs structure and formatting. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Harish Kasiviswanathan <harish.kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
57 lines
2.1 KiB
C
57 lines
2.1 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _AMDGPU_PMU_H_
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#define _AMDGPU_PMU_H_
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/* PMU types. */
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enum amdgpu_pmu_perf_type {
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AMDGPU_PMU_PERF_TYPE_NONE = 0,
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AMDGPU_PMU_PERF_TYPE_DF,
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AMDGPU_PMU_PERF_TYPE_ALL
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};
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/*
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* PMU type AMDGPU_PMU_PERF_TYPE_ALL can hold events of different "type"
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* configurations. Event config types are parsed from the 64-bit raw
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* config (See EVENT_CONFIG_TYPE_SHIFT and EVENT_CONFIG_TYPE_MASK) and
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* are registered into the HW perf events config_base.
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*
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* PMU types with only a single event configuration type
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* (non-AMDGPU_PMU_PERF_TYPE_ALL) have their event config type auto generated
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* when the performance counter is added.
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*/
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enum amdgpu_pmu_event_config_type {
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AMDGPU_PMU_EVENT_CONFIG_TYPE_NONE = 0,
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AMDGPU_PMU_EVENT_CONFIG_TYPE_DF,
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AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI,
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AMDGPU_PMU_EVENT_CONFIG_TYPE_MAX
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};
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#define AMDGPU_PMU_EVENT_CONFIG_TYPE_SHIFT 56
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#define AMDGPU_PMU_EVENT_CONFIG_TYPE_MASK 0xff
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int amdgpu_pmu_init(struct amdgpu_device *adev);
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void amdgpu_pmu_fini(struct amdgpu_device *adev);
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#endif /* _AMDGPU_PMU_H_ */
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