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![Andy Shevchenko](/assets/img/avatar_default.png)
It's possible that PCI device can provide an IO port resource for the device. regmap MMIO currently uses MMIO by default. With an additional flag we enable support for IO port accesses. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
237 lines
6.4 KiB
C
237 lines
6.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* GPIO driver for Exar XR17V35X chip
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*
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* Copyright (C) 2015 Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/gpio/driver.h>
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#include <linux/idr.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#define EXAR_OFFSET_MPIOLVL_LO 0x90
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#define EXAR_OFFSET_MPIOSEL_LO 0x93
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#define EXAR_OFFSET_MPIOLVL_HI 0x96
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#define EXAR_OFFSET_MPIOSEL_HI 0x99
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/*
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* The Device Configuration and UART Configuration Registers
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* for each UART channel take 1KB of memory address space.
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*/
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#define EXAR_UART_CHANNEL_SIZE 0x400
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#define DRIVER_NAME "gpio_exar"
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static DEFINE_IDA(ida_index);
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struct exar_gpio_chip {
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struct gpio_chip gpio_chip;
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struct regmap *regmap;
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int index;
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char name[20];
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unsigned int first_pin;
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/*
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* The offset to the cascaded device's (if existing)
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* Device Configuration Registers.
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*/
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unsigned int cascaded_offset;
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};
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static unsigned int
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exar_offset_to_sel_addr(struct exar_gpio_chip *exar_gpio, unsigned int offset)
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{
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unsigned int pin = exar_gpio->first_pin + (offset % 16);
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unsigned int cascaded = offset / 16;
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unsigned int addr = pin / 8 ? EXAR_OFFSET_MPIOSEL_HI : EXAR_OFFSET_MPIOSEL_LO;
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return addr + (cascaded ? exar_gpio->cascaded_offset : 0);
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}
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static unsigned int
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exar_offset_to_lvl_addr(struct exar_gpio_chip *exar_gpio, unsigned int offset)
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{
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unsigned int pin = exar_gpio->first_pin + (offset % 16);
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unsigned int cascaded = offset / 16;
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unsigned int addr = pin / 8 ? EXAR_OFFSET_MPIOLVL_HI : EXAR_OFFSET_MPIOLVL_LO;
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return addr + (cascaded ? exar_gpio->cascaded_offset : 0);
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}
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static unsigned int
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exar_offset_to_bit(struct exar_gpio_chip *exar_gpio, unsigned int offset)
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{
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unsigned int pin = exar_gpio->first_pin + (offset % 16);
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return pin % 8;
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}
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static int exar_get_direction(struct gpio_chip *chip, unsigned int offset)
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{
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struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
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unsigned int addr = exar_offset_to_sel_addr(exar_gpio, offset);
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unsigned int bit = exar_offset_to_bit(exar_gpio, offset);
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if (regmap_test_bits(exar_gpio->regmap, addr, BIT(bit)))
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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static int exar_get_value(struct gpio_chip *chip, unsigned int offset)
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{
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struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
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unsigned int addr = exar_offset_to_lvl_addr(exar_gpio, offset);
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unsigned int bit = exar_offset_to_bit(exar_gpio, offset);
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return !!(regmap_test_bits(exar_gpio->regmap, addr, BIT(bit)));
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}
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static void exar_set_value(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
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unsigned int addr = exar_offset_to_lvl_addr(exar_gpio, offset);
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unsigned int bit = exar_offset_to_bit(exar_gpio, offset);
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if (value)
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regmap_set_bits(exar_gpio->regmap, addr, BIT(bit));
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else
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regmap_clear_bits(exar_gpio->regmap, addr, BIT(bit));
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}
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static int exar_direction_output(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
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unsigned int addr = exar_offset_to_sel_addr(exar_gpio, offset);
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unsigned int bit = exar_offset_to_bit(exar_gpio, offset);
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exar_set_value(chip, offset, value);
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regmap_clear_bits(exar_gpio->regmap, addr, BIT(bit));
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return 0;
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}
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static int exar_direction_input(struct gpio_chip *chip, unsigned int offset)
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{
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struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
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unsigned int addr = exar_offset_to_sel_addr(exar_gpio, offset);
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unsigned int bit = exar_offset_to_bit(exar_gpio, offset);
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regmap_set_bits(exar_gpio->regmap, addr, BIT(bit));
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return 0;
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}
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static void exar_devm_ida_free(void *data)
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{
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struct exar_gpio_chip *exar_gpio = data;
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ida_free(&ida_index, exar_gpio->index);
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}
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static const struct regmap_config exar_regmap_config = {
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.name = "exar-gpio",
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.reg_bits = 16,
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.val_bits = 8,
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.io_port = true,
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};
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static int gpio_exar_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct pci_dev *pcidev = to_pci_dev(dev->parent);
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struct exar_gpio_chip *exar_gpio;
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u32 first_pin, ngpios;
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void __iomem *p;
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int index, ret;
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/*
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* The UART driver must have mapped region 0 prior to registering this
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* device - use it.
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*/
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p = pcim_iomap_table(pcidev)[0];
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if (!p)
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return -ENOMEM;
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ret = device_property_read_u32(dev, "exar,first-pin", &first_pin);
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if (ret)
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return ret;
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ret = device_property_read_u32(dev, "ngpios", &ngpios);
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if (ret)
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return ret;
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exar_gpio = devm_kzalloc(dev, sizeof(*exar_gpio), GFP_KERNEL);
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if (!exar_gpio)
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return -ENOMEM;
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/*
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* If cascaded, secondary xr17v354 or xr17v358 have the same amount
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* of MPIOs as their primaries and the last 4 bits of the primary's
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* PCI Device ID is the number of its UART channels.
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*/
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if (pcidev->device & GENMASK(15, 12)) {
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ngpios += ngpios;
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exar_gpio->cascaded_offset = (pcidev->device & GENMASK(3, 0)) *
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EXAR_UART_CHANNEL_SIZE;
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}
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/*
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* We don't need to check the return values of mmio regmap operations (unless
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* the regmap has a clock attached which is not the case here).
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*/
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exar_gpio->regmap = devm_regmap_init_mmio(dev, p, &exar_regmap_config);
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if (IS_ERR(exar_gpio->regmap))
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return PTR_ERR(exar_gpio->regmap);
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index = ida_alloc(&ida_index, GFP_KERNEL);
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if (index < 0)
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return index;
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ret = devm_add_action_or_reset(dev, exar_devm_ida_free, exar_gpio);
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if (ret)
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return ret;
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sprintf(exar_gpio->name, "exar_gpio%d", index);
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exar_gpio->gpio_chip.label = exar_gpio->name;
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exar_gpio->gpio_chip.parent = dev;
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exar_gpio->gpio_chip.direction_output = exar_direction_output;
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exar_gpio->gpio_chip.direction_input = exar_direction_input;
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exar_gpio->gpio_chip.get_direction = exar_get_direction;
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exar_gpio->gpio_chip.get = exar_get_value;
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exar_gpio->gpio_chip.set = exar_set_value;
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exar_gpio->gpio_chip.base = -1;
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exar_gpio->gpio_chip.ngpio = ngpios;
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exar_gpio->index = index;
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exar_gpio->first_pin = first_pin;
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ret = devm_gpiochip_add_data(dev, &exar_gpio->gpio_chip, exar_gpio);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, exar_gpio);
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return 0;
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}
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static struct platform_driver gpio_exar_driver = {
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.probe = gpio_exar_probe,
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.driver = {
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.name = DRIVER_NAME,
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},
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};
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module_platform_driver(gpio_exar_driver);
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MODULE_ALIAS("platform:" DRIVER_NAME);
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MODULE_DESCRIPTION("Exar GPIO driver");
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MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
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MODULE_LICENSE("GPL");
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