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03d576f202
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced from ldb_di_clk. To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the switch. As this can not be guaranteed by the clock framework during runtime, make the ldb_di[x]_sel muxes read-only. A workaround to set the muxes once during boot could be added to the kernel or bootloader. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> |
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.. | ||
clk-busy.c | ||
clk-cpu.c | ||
clk-fixup-div.c | ||
clk-fixup-mux.c | ||
clk-gate-exclusive.c | ||
clk-gate2.c | ||
clk-imx1.c | ||
clk-imx6q.c | ||
clk-imx6sl.c | ||
clk-imx6sx.c | ||
clk-imx6ul.c | ||
clk-imx7d.c | ||
clk-imx21.c | ||
clk-imx25.c | ||
clk-imx27.c | ||
clk-imx31.c | ||
clk-imx35.c | ||
clk-imx51-imx53.c | ||
clk-pfd.c | ||
clk-pllv1.c | ||
clk-pllv2.c | ||
clk-pllv3.c | ||
clk-vf610.c | ||
clk.c | ||
clk.h | ||
Makefile |