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44d1b980c7
Although if people have questions about ARCnet, perhaps it's _better_ for them to be mailing dwmw2@cam.ac.uk about it... Signed-off-by: David Woodhouse <dwmw2@infradead.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
373 lines
9.6 KiB
ArmAsm
373 lines
9.6 KiB
ArmAsm
/* sleep.S: power saving mode entry
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Woodhouse (dwmw2@infradead.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/sys.h>
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#include <linux/linkage.h>
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#include <asm/setup.h>
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#include <asm/segment.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include <asm/errno.h>
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#include <asm/cache.h>
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#include <asm/spr-regs.h>
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#define __addr_MASK 0xfeff9820 /* interrupt controller mask */
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#define __addr_FR55X_DRCN 0xfeff0218 /* Address of DRCN register */
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#define FR55X_DSTS_OFFSET -4 /* Offset from DRCN to DSTS */
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#define FR55X_SDRAMC_DSTS_SSI 0x00000002 /* indicates that the SDRAM is in self-refresh mode */
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#define __addr_FR4XX_DRCN 0xfe000430 /* Address of DRCN register */
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#define FR4XX_DSTS_OFFSET -8 /* Offset from DRCN to DSTS */
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#define FR4XX_SDRAMC_DSTS_SSI 0x00000001 /* indicates that the SDRAM is in self-refresh mode */
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#define SDRAMC_DRCN_SR 0x00000001 /* transition SDRAM into self-refresh mode */
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.section .bss
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.balign 8
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.globl __sleep_save_area
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__sleep_save_area:
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.space 16
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.text
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.balign 4
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.macro li v r
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sethi.p %hi(\v),\r
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setlo %lo(\v),\r
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.endm
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#ifdef CONFIG_PM
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###############################################################################
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#
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# CPU suspension routine
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# - void frv_cpu_suspend(unsigned long pdm_mode)
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#
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###############################################################################
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.globl frv_cpu_suspend
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.type frv_cpu_suspend,@function
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frv_cpu_suspend:
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#----------------------------------------------------
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# save hsr0, psr, isr, and lr for resume code
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#----------------------------------------------------
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li __sleep_save_area,gr11
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movsg hsr0,gr4
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movsg psr,gr5
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movsg isr,gr6
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movsg lr,gr7
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stdi gr4,@(gr11,#0)
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stdi gr6,@(gr11,#8)
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# store the return address from sleep in GR14, and its complement in GR13 as a check
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li __ramboot_resume,gr14
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#ifdef CONFIG_MMU
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# Resume via RAMBOOT# will turn MMU off, so bootloader needs a physical address.
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sethi.p %hi(__page_offset),gr13
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setlo %lo(__page_offset),gr13
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sub gr14,gr13,gr14
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#endif
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not gr14,gr13
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#----------------------------------------------------
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# preload and lock into icache that code which may have to run
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# when dram is in self-refresh state.
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#----------------------------------------------------
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movsg hsr0, gr3
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li HSR0_ICE,gr4
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or gr3,gr4,gr3
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movgs gr3,hsr0
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or gr3,gr8,gr7 // add the sleep bits for later
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li #__icache_lock_start,gr3
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li #__icache_lock_end,gr4
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1: icpl gr3,gr0,#1
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addi gr3,#L1_CACHE_BYTES,gr3
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cmp gr4,gr3,icc0
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bhi icc0,#0,1b
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# disable exceptions
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movsg psr,gr8
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andi.p gr8,#~PSR_PIL,gr8
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andi gr8,~PSR_ET,gr8
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movgs gr8,psr
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ori gr8,#PSR_ET,gr8
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srli gr8,#28,gr4
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subicc gr4,#3,gr0,icc0
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beq icc0,#0,1f
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# FR4xx
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li __addr_FR4XX_DRCN,gr4
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li FR4XX_SDRAMC_DSTS_SSI,gr5
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li FR4XX_DSTS_OFFSET,gr6
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bra __icache_lock_start
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1:
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# FR5xx
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li __addr_FR55X_DRCN,gr4
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li FR55X_SDRAMC_DSTS_SSI,gr5
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li FR55X_DSTS_OFFSET,gr6
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bra __icache_lock_start
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.size frv_cpu_suspend, .-frv_cpu_suspend
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#
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# the final part of the sleep sequence...
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# - we want it to be be cacheline aligned so we can lock it into the icache easily
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# On entry: gr7 holds desired hsr0 sleep value
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# gr8 holds desired psr sleep value
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#
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.balign L1_CACHE_BYTES
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.type __icache_lock_start,@function
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__icache_lock_start:
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#----------------------------------------------------
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# put SDRAM in self-refresh mode
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#----------------------------------------------------
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# Flush all data in the cache using the DCEF instruction.
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dcef @(gr0,gr0),#1
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# Stop DMAC transfer
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# Execute dummy load from SDRAM
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ldi @(gr11,#0),gr11
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# put the SDRAM into self-refresh mode
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ld @(gr4,gr0),gr11
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ori gr11,#SDRAMC_DRCN_SR,gr11
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st gr11,@(gr4,gr0)
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membar
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# wait for SDRAM to reach self-refresh mode
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1: ld @(gr4,gr6),gr11
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andcc gr11,gr5,gr11,icc0
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beq icc0,#0,1b
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# Set the GPIO register so that the IRQ[3:0] pins become valid, as required.
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# Set the clock mode (CLKC register) as required.
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# - At this time, also set the CLKC register P0 bit.
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# Set the HSR0 register PDM field.
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movgs gr7,hsr0
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# Execute NOP 32 times.
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.rept 32
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nop
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.endr
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#if 0 // Fujitsu recommend to skip this and will update docs.
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# Release the interrupt mask setting of the MASK register of the
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# interrupt controller if necessary.
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sti gr10,@(gr9,#0)
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membar
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#endif
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# Set the PSR register ET bit to 1 to enable interrupts.
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movgs gr8,psr
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###################################################
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# this is only reached if waking up via interrupt
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###################################################
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# Execute NOP 32 times.
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.rept 32
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nop
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.endr
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#----------------------------------------------------
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# wake SDRAM from self-refresh mode
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#----------------------------------------------------
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ld @(gr4,gr0),gr11
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andi gr11,#~SDRAMC_DRCN_SR,gr11
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st gr11,@(gr4,gr0)
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membar
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2:
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ld @(gr4,gr6),gr11 // Wait for it to come back...
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andcc gr11,gr5,gr0,icc0
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bne icc0,0,2b
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# wait for the SDRAM to stabilise
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li 0x0100000,gr3
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3: subicc gr3,#1,gr3,icc0
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bne icc0,#0,3b
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# now that DRAM is back, this is the end of the code which gets
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# locked in icache.
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__icache_lock_end:
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.size __icache_lock_start, .-__icache_lock_start
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# Fall-through to the RAMBOOT# wakeup path
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###############################################################################
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#
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# resume from suspend re-entry point reached via RAMBOOT# and bootloader
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#
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###############################################################################
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__ramboot_resume:
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#----------------------------------------------------
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# restore hsr0, psr, isr, and leave saved lr in gr7
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#----------------------------------------------------
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li __sleep_save_area,gr11
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#ifdef CONFIG_MMU
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movsg hsr0,gr4
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sethi.p %hi(HSR0_EXMMU),gr3
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setlo %lo(HSR0_EXMMU),gr3
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andcc gr3,gr4,gr0,icc0
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bne icc0,#0,2f
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# need to use physical address
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sethi.p %hi(__page_offset),gr3
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setlo %lo(__page_offset),gr3
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sub gr11,gr3,gr11
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# flush all tlb entries
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setlos #64,gr4
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setlos.p #PAGE_SIZE,gr5
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setlos #0,gr6
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1:
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tlbpr gr6,gr0,#6,#0
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subicc.p gr4,#1,gr4,icc0
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add gr6,gr5,gr6
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bne icc0,#2,1b
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# need a temporary mapping for the current physical address we are
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# using between time MMU is enabled and jump to virtual address is
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# made.
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sethi.p %hi(0x00000000),gr4
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setlo %lo(0x00000000),gr4 ; physical address
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setlos #xAMPRx_L|xAMPRx_M|xAMPRx_SS_256Mb|xAMPRx_S_KERNEL|xAMPRx_V,gr5
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or gr4,gr5,gr5
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movsg cxnr,gr13
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or gr4,gr13,gr4
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movgs gr4,iamlr1 ; mapped from real address 0
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movgs gr5,iampr1 ; cached kernel memory at 0x00000000
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2:
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#endif
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lddi @(gr11,#0),gr4 ; hsr0, psr
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lddi @(gr11,#8),gr6 ; isr, lr
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movgs gr4,hsr0
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bar
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#ifdef CONFIG_MMU
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sethi.p %hi(1f),gr11
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setlo %lo(1f),gr11
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jmpl @(gr11,gr0)
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1:
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movgs gr0,iampr1 ; get rid of temporary mapping
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#endif
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movgs gr5,psr
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movgs gr6,isr
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#----------------------------------------------------
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# unlock the icache which was locked before going to sleep
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#----------------------------------------------------
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li __icache_lock_start,gr3
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li __icache_lock_end,gr4
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1: icul gr3
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addi gr3,#L1_CACHE_BYTES,gr3
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cmp gr4,gr3,icc0
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bhi icc0,#0,1b
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#----------------------------------------------------
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# back to business as usual
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#----------------------------------------------------
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jmpl @(gr7,gr0) ;
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#endif /* CONFIG_PM */
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###############################################################################
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#
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# CPU core sleep mode routine
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#
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###############################################################################
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.globl frv_cpu_core_sleep
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.type frv_cpu_core_sleep,@function
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frv_cpu_core_sleep:
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# Preload into icache.
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li #__core_sleep_icache_lock_start,gr3
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li #__core_sleep_icache_lock_end,gr4
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1: icpl gr3,gr0,#1
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addi gr3,#L1_CACHE_BYTES,gr3
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cmp gr4,gr3,icc0
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bhi icc0,#0,1b
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bra __core_sleep_icache_lock_start
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.balign L1_CACHE_BYTES
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__core_sleep_icache_lock_start:
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# (1) Set the PSR register ET bit to 0 to disable interrupts.
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movsg psr,gr8
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andi.p gr8,#~(PSR_PIL),gr8
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andi gr8,#~(PSR_ET),gr4
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movgs gr4,psr
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#if 0 // Fujitsu recommend to skip this and will update docs.
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# (2) Set '1' to all bits in the MASK register of the interrupt
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# controller and mask interrupts.
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sethi.p %hi(__addr_MASK),gr9
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setlo %lo(__addr_MASK),gr9
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sethi.p %hi(0xffff0000),gr4
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setlo %lo(0xffff0000),gr4
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ldi @(gr9,#0),gr10
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sti gr4,@(gr9,#0)
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#endif
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# (3) Flush all data in the cache using the DCEF instruction.
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dcef @(gr0,gr0),#1
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# (4) Execute the memory barrier instruction
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membar
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# (5) Set the GPIO register so that the IRQ[3:0] pins become valid, as required.
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# (6) Set the clock mode (CLKC register) as required.
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# - At this time, also set the CLKC register P0 bit.
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# (7) Set the HSR0 register PDM field to 001 .
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movsg hsr0,gr4
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ori gr4,HSR0_PDM_CORE_SLEEP,gr4
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movgs gr4,hsr0
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# (8) Execute NOP 32 times.
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.rept 32
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nop
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.endr
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#if 0 // Fujitsu recommend to skip this and will update docs.
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# (9) Release the interrupt mask setting of the MASK register of the
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# interrupt controller if necessary.
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sti gr10,@(gr9,#0)
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membar
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#endif
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# (10) Set the PSR register ET bit to 1 to enable interrupts.
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movgs gr8,psr
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__core_sleep_icache_lock_end:
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# Unlock from icache
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li __core_sleep_icache_lock_start,gr3
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li __core_sleep_icache_lock_end,gr4
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1: icul gr3
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addi gr3,#L1_CACHE_BYTES,gr3
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cmp gr4,gr3,icc0
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bhi icc0,#0,1b
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bralr
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.size frv_cpu_core_sleep, .-frv_cpu_core_sleep
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