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![Andrew Lunn](/assets/img/avatar_default.png)
Armada 370/XP devices can 'blink' GPIO lines with a configurable on and off period. This can be modelled as a PWM. However, there are only two sets of PWM configuration registers for all the GPIO lines. This driver simply allows a single GPIO line per GPIO chip of 32 lines to be used as a PWM. Attempts to use more return EBUSY. Due to the interleaving of registers it is not simple to separate the PWM driver from the GPIO driver. Thus the GPIO driver has been extended with a PWM driver. Signed-off-by: Andrew Lunn <andrew@lunn.ch> URL: https://patchwork.ozlabs.org/patch/427287/ URL: https://patchwork.ozlabs.org/patch/427295/ [Ralph Sennhauser: * Port forward * Merge PWM portion into gpio-mvebu.c * Switch to atomic PWM API * Add new compatible string marvell,armada-370-xp-gpio * Update and merge documentation patch * Update MAINTAINERS] Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
1145 lines
30 KiB
C
1145 lines
30 KiB
C
/*
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* GPIO driver for Marvell SoCs
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*
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* Copyright (C) 2012 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Andrew Lunn <andrew@lunn.ch>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* This driver is a fairly straightforward GPIO driver for the
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* complete family of Marvell EBU SoC platforms (Orion, Dove,
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* Kirkwood, Discovery, Armada 370/XP). The only complexity of this
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* driver is the different register layout that exists between the
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* non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
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* platforms (MV78200 from the Discovery family and the Armada
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* XP). Therefore, this driver handles three variants of the GPIO
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* block:
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* - the basic variant, called "orion-gpio", with the simplest
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* register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
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* non-SMP Discovery systems
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* - the mv78200 variant for MV78200 Discovery systems. This variant
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* turns the edge mask and level mask registers into CPU0 edge
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* mask/level mask registers, and adds CPU1 edge mask/level mask
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* registers.
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* - the armadaxp variant for Armada XP systems. This variant keeps
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* the normal cause/edge mask/level mask registers when the global
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* interrupts are used, but adds per-CPU cause/edge mask/level mask
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* registers n a separate memory area for the per-CPU GPIO
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* interrupts.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/gpio.h>
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#include <linux/irq.h>
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#include <linux/slab.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/of_irq.h>
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#include <linux/of_device.h>
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#include <linux/pwm.h>
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#include <linux/clk.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/platform_device.h>
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#include <linux/bitops.h>
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#include "gpiolib.h"
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/*
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* GPIO unit register offsets.
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*/
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#define GPIO_OUT_OFF 0x0000
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#define GPIO_IO_CONF_OFF 0x0004
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#define GPIO_BLINK_EN_OFF 0x0008
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#define GPIO_IN_POL_OFF 0x000c
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#define GPIO_DATA_IN_OFF 0x0010
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#define GPIO_EDGE_CAUSE_OFF 0x0014
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#define GPIO_EDGE_MASK_OFF 0x0018
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#define GPIO_LEVEL_MASK_OFF 0x001c
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#define GPIO_BLINK_CNT_SELECT_OFF 0x0020
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/*
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* PWM register offsets.
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*/
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#define PWM_BLINK_ON_DURATION_OFF 0x0
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#define PWM_BLINK_OFF_DURATION_OFF 0x4
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/* The MV78200 has per-CPU registers for edge mask and level mask */
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#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
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#define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
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/*
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* The Armada XP has per-CPU registers for interrupt cause, interrupt
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* mask and interrupt level mask. Those are relative to the
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* percpu_membase.
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*/
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#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
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#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
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#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
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#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
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#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
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#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
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#define MVEBU_MAX_GPIO_PER_BANK 32
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struct mvebu_pwm {
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void __iomem *membase;
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unsigned long clk_rate;
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struct gpio_desc *gpiod;
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struct pwm_chip chip;
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spinlock_t lock;
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struct mvebu_gpio_chip *mvchip;
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/* Used to preserve GPIO/PWM registers across suspend/resume */
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u32 blink_select;
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u32 blink_on_duration;
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u32 blink_off_duration;
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};
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struct mvebu_gpio_chip {
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struct gpio_chip chip;
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spinlock_t lock;
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void __iomem *membase;
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void __iomem *percpu_membase;
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int irqbase;
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struct irq_domain *domain;
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int soc_variant;
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/* Used for PWM support */
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struct clk *clk;
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struct mvebu_pwm *mvpwm;
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/* Used to preserve GPIO registers across suspend/resume */
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u32 out_reg;
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u32 io_conf_reg;
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u32 blink_en_reg;
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u32 in_pol_reg;
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u32 edge_mask_regs[4];
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u32 level_mask_regs[4];
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};
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/*
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* Functions returning addresses of individual registers for a given
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* GPIO controller.
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*/
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static void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_OUT_OFF;
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}
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static void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_BLINK_EN_OFF;
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}
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static void __iomem *mvebu_gpioreg_blink_counter_select(struct mvebu_gpio_chip
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*mvchip)
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{
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return mvchip->membase + GPIO_BLINK_CNT_SELECT_OFF;
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}
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static void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_IO_CONF_OFF;
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}
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static void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_IN_POL_OFF;
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}
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static void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_DATA_IN_OFF;
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}
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static void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
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{
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int cpu;
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switch (mvchip->soc_variant) {
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case MVEBU_GPIO_SOC_VARIANT_ORION:
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case MVEBU_GPIO_SOC_VARIANT_MV78200:
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return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
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case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
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cpu = smp_processor_id();
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return mvchip->percpu_membase +
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GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
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default:
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BUG();
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}
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}
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static void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
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{
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int cpu;
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switch (mvchip->soc_variant) {
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case MVEBU_GPIO_SOC_VARIANT_ORION:
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return mvchip->membase + GPIO_EDGE_MASK_OFF;
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case MVEBU_GPIO_SOC_VARIANT_MV78200:
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cpu = smp_processor_id();
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return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
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case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
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cpu = smp_processor_id();
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return mvchip->percpu_membase +
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GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
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default:
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BUG();
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}
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}
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static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip)
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{
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int cpu;
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switch (mvchip->soc_variant) {
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case MVEBU_GPIO_SOC_VARIANT_ORION:
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return mvchip->membase + GPIO_LEVEL_MASK_OFF;
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case MVEBU_GPIO_SOC_VARIANT_MV78200:
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cpu = smp_processor_id();
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return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
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case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
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cpu = smp_processor_id();
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return mvchip->percpu_membase +
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GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
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default:
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BUG();
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}
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}
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/*
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* Functions returning addresses of individual registers for a given
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* PWM controller.
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*/
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static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
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{
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return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF;
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}
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static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
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{
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return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF;
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}
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/*
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* Functions implementing the gpio_chip methods
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*/
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static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
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{
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struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
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unsigned long flags;
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u32 u;
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spin_lock_irqsave(&mvchip->lock, flags);
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u = readl_relaxed(mvebu_gpioreg_out(mvchip));
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if (value)
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u |= BIT(pin);
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else
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u &= ~BIT(pin);
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writel_relaxed(u, mvebu_gpioreg_out(mvchip));
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spin_unlock_irqrestore(&mvchip->lock, flags);
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}
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static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
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{
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struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
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u32 u;
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if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & BIT(pin)) {
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u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
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readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
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} else {
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u = readl_relaxed(mvebu_gpioreg_out(mvchip));
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}
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return (u >> pin) & 1;
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}
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static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
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int value)
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{
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struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
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unsigned long flags;
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u32 u;
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spin_lock_irqsave(&mvchip->lock, flags);
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u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
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if (value)
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u |= BIT(pin);
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else
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u &= ~BIT(pin);
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writel_relaxed(u, mvebu_gpioreg_blink(mvchip));
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spin_unlock_irqrestore(&mvchip->lock, flags);
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}
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static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
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{
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struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
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unsigned long flags;
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int ret;
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u32 u;
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/*
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* Check with the pinctrl driver whether this pin is usable as
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* an input GPIO
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*/
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ret = pinctrl_gpio_direction_input(chip->base + pin);
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if (ret)
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return ret;
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spin_lock_irqsave(&mvchip->lock, flags);
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u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
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u |= BIT(pin);
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writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
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spin_unlock_irqrestore(&mvchip->lock, flags);
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return 0;
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}
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static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
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int value)
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{
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struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
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unsigned long flags;
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int ret;
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u32 u;
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/*
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* Check with the pinctrl driver whether this pin is usable as
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* an output GPIO
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*/
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ret = pinctrl_gpio_direction_output(chip->base + pin);
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if (ret)
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return ret;
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mvebu_gpio_blink(chip, pin, 0);
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mvebu_gpio_set(chip, pin, value);
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spin_lock_irqsave(&mvchip->lock, flags);
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u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
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u &= ~BIT(pin);
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writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
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spin_unlock_irqrestore(&mvchip->lock, flags);
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return 0;
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}
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static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
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{
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struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
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return irq_create_mapping(mvchip->domain, pin);
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}
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/*
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* Functions implementing the irq_chip methods
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*/
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static void mvebu_gpio_irq_ack(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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u32 mask = d->mask;
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irq_gc_lock(gc);
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writel_relaxed(~mask, mvebu_gpioreg_edge_cause(mvchip));
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irq_gc_unlock(gc);
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}
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static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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u32 mask = d->mask;
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irq_gc_lock(gc);
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ct->mask_cache_priv &= ~mask;
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writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
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irq_gc_unlock(gc);
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}
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static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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u32 mask = d->mask;
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irq_gc_lock(gc);
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ct->mask_cache_priv |= mask;
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writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
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irq_gc_unlock(gc);
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}
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static void mvebu_gpio_level_irq_mask(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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u32 mask = d->mask;
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irq_gc_lock(gc);
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ct->mask_cache_priv &= ~mask;
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writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
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irq_gc_unlock(gc);
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}
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static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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u32 mask = d->mask;
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irq_gc_lock(gc);
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ct->mask_cache_priv |= mask;
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writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
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irq_gc_unlock(gc);
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}
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/*****************************************************************************
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* MVEBU GPIO IRQ
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*
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* GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
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* value of the line or the opposite value.
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*
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* Level IRQ handlers: DATA_IN is used directly as cause register.
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* Interrupt are masked by LEVEL_MASK registers.
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* Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
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* Interrupt are masked by EDGE_MASK registers.
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* Both-edge handlers: Similar to regular Edge handlers, but also swaps
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* the polarity to catch the next line transaction.
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* This is a race condition that might not perfectly
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* work on some use cases.
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*
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* Every eight GPIO lines are grouped (OR'ed) before going up to main
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* cause register.
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*
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* EDGE cause mask
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* data-in /--------| |-----| |----\
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* -----| |----- ---- to main cause reg
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* X \----------------| |----/
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* polarity LEVEL mask
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*
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****************************************************************************/
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static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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int pin;
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u32 u;
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pin = d->hwirq;
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u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & BIT(pin);
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if (!u)
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return -EINVAL;
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type &= IRQ_TYPE_SENSE_MASK;
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if (type == IRQ_TYPE_NONE)
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|
return -EINVAL;
|
|
|
|
/* Check if we need to change chip and handler */
|
|
if (!(ct->type & type))
|
|
if (irq_setup_alt_chip(d, type))
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* Configure interrupt polarity.
|
|
*/
|
|
switch (type) {
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
case IRQ_TYPE_LEVEL_HIGH:
|
|
u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
|
|
u &= ~BIT(pin);
|
|
writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
|
|
break;
|
|
case IRQ_TYPE_EDGE_FALLING:
|
|
case IRQ_TYPE_LEVEL_LOW:
|
|
u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
|
|
u |= BIT(pin);
|
|
writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
|
|
break;
|
|
case IRQ_TYPE_EDGE_BOTH: {
|
|
u32 v;
|
|
|
|
v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^
|
|
readl_relaxed(mvebu_gpioreg_data_in(mvchip));
|
|
|
|
/*
|
|
* set initial polarity based on current input level
|
|
*/
|
|
u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
|
|
if (v & BIT(pin))
|
|
u |= BIT(pin); /* falling */
|
|
else
|
|
u &= ~BIT(pin); /* rising */
|
|
writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
|
|
break;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void mvebu_gpio_irq_handler(struct irq_desc *desc)
|
|
{
|
|
struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
u32 cause, type;
|
|
int i;
|
|
|
|
if (mvchip == NULL)
|
|
return;
|
|
|
|
chained_irq_enter(chip, desc);
|
|
|
|
cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
|
|
readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
|
|
cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
|
|
readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
|
|
|
|
for (i = 0; i < mvchip->chip.ngpio; i++) {
|
|
int irq;
|
|
|
|
irq = irq_find_mapping(mvchip->domain, i);
|
|
|
|
if (!(cause & BIT(i)))
|
|
continue;
|
|
|
|
type = irq_get_trigger_type(irq);
|
|
if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
|
|
/* Swap polarity (race with GPIO line) */
|
|
u32 polarity;
|
|
|
|
polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
|
|
polarity ^= BIT(i);
|
|
writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
|
|
}
|
|
|
|
generic_handle_irq(irq);
|
|
}
|
|
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
/*
|
|
* Functions implementing the pwm_chip methods
|
|
*/
|
|
static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
|
|
{
|
|
return container_of(chip, struct mvebu_pwm, chip);
|
|
}
|
|
|
|
static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
|
|
{
|
|
struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
|
|
struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
|
|
struct gpio_desc *desc;
|
|
unsigned long flags;
|
|
int ret = 0;
|
|
|
|
spin_lock_irqsave(&mvpwm->lock, flags);
|
|
|
|
if (mvpwm->gpiod) {
|
|
ret = -EBUSY;
|
|
} else {
|
|
desc = gpio_to_desc(mvchip->chip.base + pwm->hwpwm);
|
|
if (!desc) {
|
|
ret = -ENODEV;
|
|
goto out;
|
|
}
|
|
|
|
ret = gpiod_request(desc, "mvebu-pwm");
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = gpiod_direction_output(desc, 0);
|
|
if (ret) {
|
|
gpiod_free(desc);
|
|
goto out;
|
|
}
|
|
|
|
mvpwm->gpiod = desc;
|
|
}
|
|
out:
|
|
spin_unlock_irqrestore(&mvpwm->lock, flags);
|
|
return ret;
|
|
}
|
|
|
|
static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
|
|
{
|
|
struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&mvpwm->lock, flags);
|
|
gpiod_free(mvpwm->gpiod);
|
|
mvpwm->gpiod = NULL;
|
|
spin_unlock_irqrestore(&mvpwm->lock, flags);
|
|
}
|
|
|
|
static void mvebu_pwm_get_state(struct pwm_chip *chip,
|
|
struct pwm_device *pwm,
|
|
struct pwm_state *state) {
|
|
|
|
struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
|
|
struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
|
|
unsigned long long val;
|
|
unsigned long flags;
|
|
u32 u;
|
|
|
|
spin_lock_irqsave(&mvpwm->lock, flags);
|
|
|
|
val = (unsigned long long)
|
|
readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
|
|
val *= NSEC_PER_SEC;
|
|
do_div(val, mvpwm->clk_rate);
|
|
if (val > UINT_MAX)
|
|
state->duty_cycle = UINT_MAX;
|
|
else if (val)
|
|
state->duty_cycle = val;
|
|
else
|
|
state->duty_cycle = 1;
|
|
|
|
val = (unsigned long long)
|
|
readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
|
|
val *= NSEC_PER_SEC;
|
|
do_div(val, mvpwm->clk_rate);
|
|
if (val < state->duty_cycle) {
|
|
state->period = 1;
|
|
} else {
|
|
val -= state->duty_cycle;
|
|
if (val > UINT_MAX)
|
|
state->period = UINT_MAX;
|
|
else if (val)
|
|
state->period = val;
|
|
else
|
|
state->period = 1;
|
|
}
|
|
|
|
u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
|
|
if (u)
|
|
state->enabled = true;
|
|
else
|
|
state->enabled = false;
|
|
|
|
spin_unlock_irqrestore(&mvpwm->lock, flags);
|
|
}
|
|
|
|
static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
|
|
struct pwm_state *state)
|
|
{
|
|
struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
|
|
struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
|
|
unsigned long long val;
|
|
unsigned long flags;
|
|
unsigned int on, off;
|
|
|
|
val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
|
|
do_div(val, NSEC_PER_SEC);
|
|
if (val > UINT_MAX)
|
|
return -EINVAL;
|
|
if (val)
|
|
on = val;
|
|
else
|
|
on = 1;
|
|
|
|
val = (unsigned long long) mvpwm->clk_rate *
|
|
(state->period - state->duty_cycle);
|
|
do_div(val, NSEC_PER_SEC);
|
|
if (val > UINT_MAX)
|
|
return -EINVAL;
|
|
if (val)
|
|
off = val;
|
|
else
|
|
off = 1;
|
|
|
|
spin_lock_irqsave(&mvpwm->lock, flags);
|
|
|
|
writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm));
|
|
writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm));
|
|
if (state->enabled)
|
|
mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
|
|
else
|
|
mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
|
|
|
|
spin_unlock_irqrestore(&mvpwm->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pwm_ops mvebu_pwm_ops = {
|
|
.request = mvebu_pwm_request,
|
|
.free = mvebu_pwm_free,
|
|
.get_state = mvebu_pwm_get_state,
|
|
.apply = mvebu_pwm_apply,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
|
|
{
|
|
struct mvebu_pwm *mvpwm = mvchip->mvpwm;
|
|
|
|
mvpwm->blink_select =
|
|
readl_relaxed(mvebu_gpioreg_blink_counter_select(mvchip));
|
|
mvpwm->blink_on_duration =
|
|
readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
|
|
mvpwm->blink_off_duration =
|
|
readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
|
|
}
|
|
|
|
static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
|
|
{
|
|
struct mvebu_pwm *mvpwm = mvchip->mvpwm;
|
|
|
|
writel_relaxed(mvpwm->blink_select,
|
|
mvebu_gpioreg_blink_counter_select(mvchip));
|
|
writel_relaxed(mvpwm->blink_on_duration,
|
|
mvebu_pwmreg_blink_on_duration(mvpwm));
|
|
writel_relaxed(mvpwm->blink_off_duration,
|
|
mvebu_pwmreg_blink_off_duration(mvpwm));
|
|
}
|
|
|
|
static int mvebu_pwm_probe(struct platform_device *pdev,
|
|
struct mvebu_gpio_chip *mvchip,
|
|
int id)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct mvebu_pwm *mvpwm;
|
|
struct resource *res;
|
|
u32 set;
|
|
|
|
if (!of_device_is_compatible(mvchip->chip.of_node,
|
|
"marvell,armada-370-xp-gpio"))
|
|
return 0;
|
|
|
|
if (IS_ERR(mvchip->clk))
|
|
return PTR_ERR(mvchip->clk);
|
|
|
|
/*
|
|
* There are only two sets of PWM configuration registers for
|
|
* all the GPIO lines on those SoCs which this driver reserves
|
|
* for the first two GPIO chips. So if the resource is missing
|
|
* we can't treat it as an error.
|
|
*/
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm");
|
|
if (!res)
|
|
return 0;
|
|
|
|
/*
|
|
* Use set A for lines of GPIO chip with id 0, B for GPIO chip
|
|
* with id 1. Don't allow further GPIO chips to be used for PWM.
|
|
*/
|
|
if (id == 0)
|
|
set = 0;
|
|
else if (id == 1)
|
|
set = U32_MAX;
|
|
else
|
|
return -EINVAL;
|
|
writel_relaxed(0, mvebu_gpioreg_blink_counter_select(mvchip));
|
|
|
|
mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
|
|
if (!mvpwm)
|
|
return -ENOMEM;
|
|
mvchip->mvpwm = mvpwm;
|
|
mvpwm->mvchip = mvchip;
|
|
|
|
mvpwm->membase = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(mvpwm->membase))
|
|
return PTR_ERR(mvpwm->membase);
|
|
|
|
mvpwm->clk_rate = clk_get_rate(mvchip->clk);
|
|
if (!mvpwm->clk_rate) {
|
|
dev_err(dev, "failed to get clock rate\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
mvpwm->chip.dev = dev;
|
|
mvpwm->chip.ops = &mvebu_pwm_ops;
|
|
mvpwm->chip.npwm = mvchip->chip.ngpio;
|
|
|
|
spin_lock_init(&mvpwm->lock);
|
|
|
|
return pwmchip_add(&mvpwm->chip);
|
|
}
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
#include <linux/seq_file.h>
|
|
|
|
static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
|
|
{
|
|
struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
|
|
u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
|
|
int i;
|
|
|
|
out = readl_relaxed(mvebu_gpioreg_out(mvchip));
|
|
io_conf = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
|
|
blink = readl_relaxed(mvebu_gpioreg_blink(mvchip));
|
|
in_pol = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
|
|
data_in = readl_relaxed(mvebu_gpioreg_data_in(mvchip));
|
|
cause = readl_relaxed(mvebu_gpioreg_edge_cause(mvchip));
|
|
edg_msk = readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
|
|
lvl_msk = readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
|
|
|
|
for (i = 0; i < chip->ngpio; i++) {
|
|
const char *label;
|
|
u32 msk;
|
|
bool is_out;
|
|
|
|
label = gpiochip_is_requested(chip, i);
|
|
if (!label)
|
|
continue;
|
|
|
|
msk = BIT(i);
|
|
is_out = !(io_conf & msk);
|
|
|
|
seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
|
|
|
|
if (is_out) {
|
|
seq_printf(s, " out %s %s\n",
|
|
out & msk ? "hi" : "lo",
|
|
blink & msk ? "(blink )" : "");
|
|
continue;
|
|
}
|
|
|
|
seq_printf(s, " in %s (act %s) - IRQ",
|
|
(data_in ^ in_pol) & msk ? "hi" : "lo",
|
|
in_pol & msk ? "lo" : "hi");
|
|
if (!((edg_msk | lvl_msk) & msk)) {
|
|
seq_puts(s, " disabled\n");
|
|
continue;
|
|
}
|
|
if (edg_msk & msk)
|
|
seq_puts(s, " edge ");
|
|
if (lvl_msk & msk)
|
|
seq_puts(s, " level");
|
|
seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
|
|
}
|
|
}
|
|
#else
|
|
#define mvebu_gpio_dbg_show NULL
|
|
#endif
|
|
|
|
static const struct of_device_id mvebu_gpio_of_match[] = {
|
|
{
|
|
.compatible = "marvell,orion-gpio",
|
|
.data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
|
|
},
|
|
{
|
|
.compatible = "marvell,mv78200-gpio",
|
|
.data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
|
|
},
|
|
{
|
|
.compatible = "marvell,armadaxp-gpio",
|
|
.data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
|
|
},
|
|
{
|
|
.compatible = "marvell,armada-370-xp-gpio",
|
|
.data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
|
|
},
|
|
{
|
|
/* sentinel */
|
|
},
|
|
};
|
|
|
|
static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
|
|
{
|
|
struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
|
|
int i;
|
|
|
|
mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip));
|
|
mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip));
|
|
mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip));
|
|
mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip));
|
|
|
|
switch (mvchip->soc_variant) {
|
|
case MVEBU_GPIO_SOC_VARIANT_ORION:
|
|
mvchip->edge_mask_regs[0] =
|
|
readl(mvchip->membase + GPIO_EDGE_MASK_OFF);
|
|
mvchip->level_mask_regs[0] =
|
|
readl(mvchip->membase + GPIO_LEVEL_MASK_OFF);
|
|
break;
|
|
case MVEBU_GPIO_SOC_VARIANT_MV78200:
|
|
for (i = 0; i < 2; i++) {
|
|
mvchip->edge_mask_regs[i] =
|
|
readl(mvchip->membase +
|
|
GPIO_EDGE_MASK_MV78200_OFF(i));
|
|
mvchip->level_mask_regs[i] =
|
|
readl(mvchip->membase +
|
|
GPIO_LEVEL_MASK_MV78200_OFF(i));
|
|
}
|
|
break;
|
|
case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
|
|
for (i = 0; i < 4; i++) {
|
|
mvchip->edge_mask_regs[i] =
|
|
readl(mvchip->membase +
|
|
GPIO_EDGE_MASK_ARMADAXP_OFF(i));
|
|
mvchip->level_mask_regs[i] =
|
|
readl(mvchip->membase +
|
|
GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
|
|
}
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
if (IS_ENABLED(CONFIG_PWM))
|
|
mvebu_pwm_suspend(mvchip);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mvebu_gpio_resume(struct platform_device *pdev)
|
|
{
|
|
struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
|
|
int i;
|
|
|
|
writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip));
|
|
writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip));
|
|
writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip));
|
|
writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip));
|
|
|
|
switch (mvchip->soc_variant) {
|
|
case MVEBU_GPIO_SOC_VARIANT_ORION:
|
|
writel(mvchip->edge_mask_regs[0],
|
|
mvchip->membase + GPIO_EDGE_MASK_OFF);
|
|
writel(mvchip->level_mask_regs[0],
|
|
mvchip->membase + GPIO_LEVEL_MASK_OFF);
|
|
break;
|
|
case MVEBU_GPIO_SOC_VARIANT_MV78200:
|
|
for (i = 0; i < 2; i++) {
|
|
writel(mvchip->edge_mask_regs[i],
|
|
mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i));
|
|
writel(mvchip->level_mask_regs[i],
|
|
mvchip->membase +
|
|
GPIO_LEVEL_MASK_MV78200_OFF(i));
|
|
}
|
|
break;
|
|
case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
|
|
for (i = 0; i < 4; i++) {
|
|
writel(mvchip->edge_mask_regs[i],
|
|
mvchip->membase +
|
|
GPIO_EDGE_MASK_ARMADAXP_OFF(i));
|
|
writel(mvchip->level_mask_regs[i],
|
|
mvchip->membase +
|
|
GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
|
|
}
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
if (IS_ENABLED(CONFIG_PWM))
|
|
mvebu_pwm_resume(mvchip);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mvebu_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
struct mvebu_gpio_chip *mvchip;
|
|
const struct of_device_id *match;
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct resource *res;
|
|
struct irq_chip_generic *gc;
|
|
struct irq_chip_type *ct;
|
|
unsigned int ngpios;
|
|
bool have_irqs;
|
|
int soc_variant;
|
|
int i, cpu, id;
|
|
int err;
|
|
|
|
match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
|
|
if (match)
|
|
soc_variant = (unsigned long) match->data;
|
|
else
|
|
soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
|
|
|
|
/* Some gpio controllers do not provide irq support */
|
|
have_irqs = of_irq_count(np) != 0;
|
|
|
|
mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
|
|
GFP_KERNEL);
|
|
if (!mvchip)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, mvchip);
|
|
|
|
if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
|
|
dev_err(&pdev->dev, "Missing ngpios OF property\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
id = of_alias_get_id(pdev->dev.of_node, "gpio");
|
|
if (id < 0) {
|
|
dev_err(&pdev->dev, "Couldn't get OF id\n");
|
|
return id;
|
|
}
|
|
|
|
mvchip->clk = devm_clk_get(&pdev->dev, NULL);
|
|
/* Not all SoCs require a clock.*/
|
|
if (!IS_ERR(mvchip->clk))
|
|
clk_prepare_enable(mvchip->clk);
|
|
|
|
mvchip->soc_variant = soc_variant;
|
|
mvchip->chip.label = dev_name(&pdev->dev);
|
|
mvchip->chip.parent = &pdev->dev;
|
|
mvchip->chip.request = gpiochip_generic_request;
|
|
mvchip->chip.free = gpiochip_generic_free;
|
|
mvchip->chip.direction_input = mvebu_gpio_direction_input;
|
|
mvchip->chip.get = mvebu_gpio_get;
|
|
mvchip->chip.direction_output = mvebu_gpio_direction_output;
|
|
mvchip->chip.set = mvebu_gpio_set;
|
|
if (have_irqs)
|
|
mvchip->chip.to_irq = mvebu_gpio_to_irq;
|
|
mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
|
|
mvchip->chip.ngpio = ngpios;
|
|
mvchip->chip.can_sleep = false;
|
|
mvchip->chip.of_node = np;
|
|
mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
|
|
|
|
spin_lock_init(&mvchip->lock);
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
mvchip->membase = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(mvchip->membase))
|
|
return PTR_ERR(mvchip->membase);
|
|
|
|
/*
|
|
* The Armada XP has a second range of registers for the
|
|
* per-CPU registers
|
|
*/
|
|
if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev,
|
|
res);
|
|
if (IS_ERR(mvchip->percpu_membase))
|
|
return PTR_ERR(mvchip->percpu_membase);
|
|
}
|
|
|
|
/*
|
|
* Mask and clear GPIO interrupts.
|
|
*/
|
|
switch (soc_variant) {
|
|
case MVEBU_GPIO_SOC_VARIANT_ORION:
|
|
writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
|
|
writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
|
|
writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
|
|
break;
|
|
case MVEBU_GPIO_SOC_VARIANT_MV78200:
|
|
writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
|
|
for (cpu = 0; cpu < 2; cpu++) {
|
|
writel_relaxed(0, mvchip->membase +
|
|
GPIO_EDGE_MASK_MV78200_OFF(cpu));
|
|
writel_relaxed(0, mvchip->membase +
|
|
GPIO_LEVEL_MASK_MV78200_OFF(cpu));
|
|
}
|
|
break;
|
|
case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
|
|
writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
|
|
writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
|
|
writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
|
|
for (cpu = 0; cpu < 4; cpu++) {
|
|
writel_relaxed(0, mvchip->percpu_membase +
|
|
GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
|
|
writel_relaxed(0, mvchip->percpu_membase +
|
|
GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
|
|
writel_relaxed(0, mvchip->percpu_membase +
|
|
GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
|
|
}
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
|
|
|
|
/* Some gpio controllers do not provide irq support */
|
|
if (!have_irqs)
|
|
return 0;
|
|
|
|
mvchip->domain =
|
|
irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
|
|
if (!mvchip->domain) {
|
|
dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
|
|
mvchip->chip.label);
|
|
return -ENODEV;
|
|
}
|
|
|
|
err = irq_alloc_domain_generic_chips(
|
|
mvchip->domain, ngpios, 2, np->name, handle_level_irq,
|
|
IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
|
|
mvchip->chip.label);
|
|
goto err_domain;
|
|
}
|
|
|
|
/*
|
|
* NOTE: The common accessors cannot be used because of the percpu
|
|
* access to the mask registers
|
|
*/
|
|
gc = irq_get_domain_generic_chip(mvchip->domain, 0);
|
|
gc->private = mvchip;
|
|
ct = &gc->chip_types[0];
|
|
ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
|
|
ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
|
|
ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
|
|
ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
|
|
ct->chip.name = mvchip->chip.label;
|
|
|
|
ct = &gc->chip_types[1];
|
|
ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
|
|
ct->chip.irq_ack = mvebu_gpio_irq_ack;
|
|
ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
|
|
ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
|
|
ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
|
|
ct->handler = handle_edge_irq;
|
|
ct->chip.name = mvchip->chip.label;
|
|
|
|
/*
|
|
* Setup the interrupt handlers. Each chip can have up to 4
|
|
* interrupt handlers, with each handler dealing with 8 GPIO
|
|
* pins.
|
|
*/
|
|
for (i = 0; i < 4; i++) {
|
|
int irq = platform_get_irq(pdev, i);
|
|
|
|
if (irq < 0)
|
|
continue;
|
|
irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
|
|
mvchip);
|
|
}
|
|
|
|
/* Armada 370/XP has simple PWM support for GPIO lines */
|
|
if (IS_ENABLED(CONFIG_PWM))
|
|
return mvebu_pwm_probe(pdev, mvchip, id);
|
|
|
|
return 0;
|
|
|
|
err_domain:
|
|
irq_domain_remove(mvchip->domain);
|
|
|
|
return err;
|
|
}
|
|
|
|
static struct platform_driver mvebu_gpio_driver = {
|
|
.driver = {
|
|
.name = "mvebu-gpio",
|
|
.of_match_table = mvebu_gpio_of_match,
|
|
},
|
|
.probe = mvebu_gpio_probe,
|
|
.suspend = mvebu_gpio_suspend,
|
|
.resume = mvebu_gpio_resume,
|
|
};
|
|
builtin_platform_driver(mvebu_gpio_driver);
|