Venkat Reddy Talla 04fac2412b soc/tegra: pmc: Add pins for Tegra194 ... Extend the Tegra194 IO pad table with additional information such as pin names and 1.8/3.3 V settings to allow a table of voltage control pins to generated from it. This is similar to what's done for older chips and is needed to support high-speed modes for SDHCI where switching the pins to 1.8V or 3.3V is necessary. Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>		2020-03-13 10:53:10 +01:00
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arc	ARCv2: IDU-intc: Add support for edge-triggered interrupts	2019-08-26 22:34:59 +05:30
at91	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
bcm2835
brcmstb	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
fsl	soc: fsl: qe: avoid IS_ERR_VALUE in ucc_fast.c	2019-12-09 13:54:37 -06:00
imx	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
mediatek	iommu/mediatek: Clean up struct mtk_smi_iommu	2019-08-30 15:57:27 +02:00
mscc	net: mscc: ocelot: export ANA, DEV and QSYS registers to include/soc/mscc	2020-01-05 23:22:33 -08:00
nps
qcom	soc: qcom: ocmem: add missing includes	2019-10-07 08:19:43 -07:00
rockchip
sa1100	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
sifive	riscv: move sifive_l2_cache.h to include/soc	2020-01-12 10:12:44 -08:00
tegra	soc/tegra: pmc: Add pins for Tegra194	2020-03-13 10:53:10 +01:00