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![Wen He](/assets/img/avatar_default.png)
Configure the display Quality of service (QoS) levels priority if the optional property node "arm,malidp-aqros-value" is defined in DTS file. QoS signaling using AQROS and AWQOS AXI interface signals, the AQROS is driven from the "RQOS" register, so needed to program the RQOS register to avoid the high resolutions flicker issue on the LS1028A platform. Signed-off-by: Wen He <wen.he_1@nxp.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190910075913.17650-2-wen.he_1@nxp.com
412 lines
11 KiB
C
412 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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*
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* (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved.
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*
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* ARM Mali DP hardware manipulation routines.
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*/
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#ifndef __MALIDP_HW_H__
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#define __MALIDP_HW_H__
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#include <linux/bitops.h>
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#include "malidp_regs.h"
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struct videomode;
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struct clk;
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/* Mali DP IP blocks */
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enum {
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MALIDP_DE_BLOCK = 0,
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MALIDP_SE_BLOCK,
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MALIDP_DC_BLOCK
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};
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/* Mali DP layer IDs */
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enum {
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DE_VIDEO1 = BIT(0),
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DE_GRAPHICS1 = BIT(1),
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DE_GRAPHICS2 = BIT(2), /* used only in DP500 */
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DE_VIDEO2 = BIT(3),
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DE_SMART = BIT(4),
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SE_MEMWRITE = BIT(5),
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};
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enum rotation_features {
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ROTATE_NONE, /* does not support rotation at all */
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ROTATE_ANY, /* supports rotation on any buffers */
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ROTATE_COMPRESSED, /* supports rotation only on compressed buffers */
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};
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struct malidp_format_id {
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u32 format; /* DRM fourcc */
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u8 layer; /* bitmask of layers supporting it */
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u8 id; /* used internally */
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};
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#define MALIDP_INVALID_FORMAT_ID 0xff
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/*
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* hide the differences between register maps
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* by using a common structure to hold the
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* base register offsets
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*/
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struct malidp_irq_map {
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u32 irq_mask; /* mask of IRQs that can be enabled in the block */
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u32 vsync_irq; /* IRQ bit used for signaling during VSYNC */
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u32 err_mask; /* mask of bits that represent errors */
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};
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struct malidp_layer {
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u16 id; /* layer ID */
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u16 base; /* address offset for the register bank */
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u16 ptr; /* address offset for the pointer register */
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u16 stride_offset; /* offset to the first stride register. */
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s16 yuv2rgb_offset; /* offset to the YUV->RGB matrix entries */
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u16 mmu_ctrl_offset; /* offset to the MMU control register */
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enum rotation_features rot; /* type of rotation supported */
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/* address offset for the AFBC decoder registers */
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u16 afbc_decoder_offset;
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};
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enum malidp_scaling_coeff_set {
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MALIDP_UPSCALING_COEFFS = 1,
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MALIDP_DOWNSCALING_1_5_COEFFS = 2,
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MALIDP_DOWNSCALING_2_COEFFS = 3,
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MALIDP_DOWNSCALING_2_75_COEFFS = 4,
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MALIDP_DOWNSCALING_4_COEFFS = 5,
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};
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struct malidp_se_config {
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u8 scale_enable : 1;
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u8 enhancer_enable : 1;
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u8 hcoeff : 3;
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u8 vcoeff : 3;
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u8 plane_src_id;
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u16 input_w, input_h;
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u16 output_w, output_h;
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u32 h_init_phase, h_delta_phase;
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u32 v_init_phase, v_delta_phase;
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};
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/* regmap features */
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#define MALIDP_REGMAP_HAS_CLEARIRQ BIT(0)
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#define MALIDP_DEVICE_AFBC_SUPPORT_SPLIT BIT(1)
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#define MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT BIT(2)
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#define MALIDP_DEVICE_AFBC_YUYV_USE_422_P2 BIT(3)
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struct malidp_hw_regmap {
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/* address offset of the DE register bank */
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/* is always 0x0000 */
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/* address offset of the DE coefficients registers */
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const u16 coeffs_base;
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/* address offset of the SE registers bank */
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const u16 se_base;
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/* address offset of the DC registers bank */
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const u16 dc_base;
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/* address offset for the output depth register */
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const u16 out_depth_base;
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/* bitmap with register map features */
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const u8 features;
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/* list of supported layers */
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const u8 n_layers;
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const struct malidp_layer *layers;
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const struct malidp_irq_map de_irq_map;
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const struct malidp_irq_map se_irq_map;
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const struct malidp_irq_map dc_irq_map;
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/* list of supported pixel formats for each layer */
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const struct malidp_format_id *pixel_formats;
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const u8 n_pixel_formats;
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/* pitch alignment requirement in bytes */
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const u8 bus_align_bytes;
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};
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/* device features */
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/* Unlike DP550/650, DP500 has 3 stride registers in its video layer. */
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#define MALIDP_DEVICE_LV_HAS_3_STRIDES BIT(0)
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struct malidp_hw_device;
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/*
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* Static structure containing hardware specific data and pointers to
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* functions that behave differently between various versions of the IP.
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*/
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struct malidp_hw {
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const struct malidp_hw_regmap map;
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/*
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* Validate the driver instance against the hardware bits
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*/
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int (*query_hw)(struct malidp_hw_device *hwdev);
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/*
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* Set the hardware into config mode, ready to accept mode changes
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*/
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void (*enter_config_mode)(struct malidp_hw_device *hwdev);
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/*
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* Tell hardware to exit configuration mode
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*/
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void (*leave_config_mode)(struct malidp_hw_device *hwdev);
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/*
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* Query if hardware is in configuration mode
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*/
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bool (*in_config_mode)(struct malidp_hw_device *hwdev);
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/*
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* Set/clear configuration valid flag for hardware parameters that can
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* be changed outside the configuration mode to the given value.
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* Hardware will use the new settings when config valid is set,
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* after the end of the current buffer scanout, and will ignore
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* any new values for those parameters if config valid flag is cleared
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*/
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void (*set_config_valid)(struct malidp_hw_device *hwdev, u8 value);
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/*
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* Set a new mode in hardware. Requires the hardware to be in
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* configuration mode before this function is called.
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*/
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void (*modeset)(struct malidp_hw_device *hwdev, struct videomode *m);
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/*
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* Calculate the required rotation memory given the active area
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* and the buffer format.
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*/
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int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h,
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u32 fmt, bool has_modifier);
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int (*se_set_scaling_coeffs)(struct malidp_hw_device *hwdev,
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struct malidp_se_config *se_config,
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struct malidp_se_config *old_config);
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long (*se_calc_mclk)(struct malidp_hw_device *hwdev,
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struct malidp_se_config *se_config,
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struct videomode *vm);
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/*
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* Enable writing to memory the content of the next frame
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* @param hwdev - malidp_hw_device structure containing the HW description
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* @param addrs - array of addresses for each plane
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* @param pitches - array of pitches for each plane
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* @param num_planes - number of planes to be written
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* @param w - width of the output frame
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* @param h - height of the output frame
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* @param fmt_id - internal format ID of output buffer
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*/
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int (*enable_memwrite)(struct malidp_hw_device *hwdev, dma_addr_t *addrs,
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s32 *pitches, int num_planes, u16 w, u16 h, u32 fmt_id,
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const s16 *rgb2yuv_coeffs);
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/*
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* Disable the writing to memory of the next frame's content.
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*/
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void (*disable_memwrite)(struct malidp_hw_device *hwdev);
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u8 features;
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};
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/* Supported variants of the hardware */
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enum {
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MALIDP_500 = 0,
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MALIDP_550,
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MALIDP_650,
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/* keep the next entry last */
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MALIDP_MAX_DEVICES
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};
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extern const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES];
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/*
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* Structure used by the driver during runtime operation.
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*/
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struct malidp_hw_device {
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struct malidp_hw *hw;
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void __iomem *regs;
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/* APB clock */
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struct clk *pclk;
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/* AXI clock */
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struct clk *aclk;
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/* main clock for display core */
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struct clk *mclk;
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/* pixel clock for display core */
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struct clk *pxlclk;
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u8 min_line_size;
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u16 max_line_size;
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u32 output_color_depth;
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/* track the device PM state */
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bool pm_suspended;
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/* track the SE memory writeback state */
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u8 mw_state;
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/* size of memory used for rotating layers, up to two banks available */
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u32 rotation_memory[2];
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/* priority level of RQOS register used for driven the ARQOS signal */
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u32 arqos_value;
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};
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static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg)
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{
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WARN_ON(hwdev->pm_suspended);
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return readl(hwdev->regs + reg);
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}
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static inline void malidp_hw_write(struct malidp_hw_device *hwdev,
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u32 value, u32 reg)
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{
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WARN_ON(hwdev->pm_suspended);
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writel(value, hwdev->regs + reg);
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}
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static inline void malidp_hw_setbits(struct malidp_hw_device *hwdev,
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u32 mask, u32 reg)
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{
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u32 data = malidp_hw_read(hwdev, reg);
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data |= mask;
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malidp_hw_write(hwdev, data, reg);
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}
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static inline void malidp_hw_clearbits(struct malidp_hw_device *hwdev,
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u32 mask, u32 reg)
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{
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u32 data = malidp_hw_read(hwdev, reg);
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data &= ~mask;
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malidp_hw_write(hwdev, data, reg);
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}
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static inline u32 malidp_get_block_base(struct malidp_hw_device *hwdev,
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u8 block)
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{
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switch (block) {
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case MALIDP_SE_BLOCK:
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return hwdev->hw->map.se_base;
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case MALIDP_DC_BLOCK:
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return hwdev->hw->map.dc_base;
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}
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return 0;
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}
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static inline void malidp_hw_disable_irq(struct malidp_hw_device *hwdev,
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u8 block, u32 irq)
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{
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u32 base = malidp_get_block_base(hwdev, block);
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malidp_hw_clearbits(hwdev, irq, base + MALIDP_REG_MASKIRQ);
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}
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static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev,
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u8 block, u32 irq)
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{
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u32 base = malidp_get_block_base(hwdev, block);
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malidp_hw_setbits(hwdev, irq, base + MALIDP_REG_MASKIRQ);
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}
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int malidp_de_irq_init(struct drm_device *drm, int irq);
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void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev);
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void malidp_de_irq_hw_init(struct malidp_hw_device *hwdev);
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void malidp_de_irq_fini(struct malidp_hw_device *hwdev);
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int malidp_se_irq_init(struct drm_device *drm, int irq);
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void malidp_se_irq_fini(struct malidp_hw_device *hwdev);
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u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
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u8 layer_id, u32 format, bool has_modifier);
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int malidp_format_get_bpp(u32 fmt);
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static inline u8 malidp_hw_get_pitch_align(struct malidp_hw_device *hwdev, bool rotated)
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{
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/*
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* only hardware that cannot do 8 bytes bus alignments have further
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* constraints on rotated planes
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*/
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if (hwdev->hw->map.bus_align_bytes == 8)
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return 8;
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else
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return hwdev->hw->map.bus_align_bytes << (rotated ? 2 : 0);
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}
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/* U16.16 */
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#define FP_1_00000 0x00010000 /* 1.0 */
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#define FP_0_66667 0x0000AAAA /* 0.6667 = 1/1.5 */
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#define FP_0_50000 0x00008000 /* 0.5 = 1/2 */
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#define FP_0_36363 0x00005D17 /* 0.36363 = 1/2.75 */
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#define FP_0_25000 0x00004000 /* 0.25 = 1/4 */
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static inline enum malidp_scaling_coeff_set
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malidp_se_select_coeffs(u32 upscale_factor)
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{
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return (upscale_factor >= FP_1_00000) ? MALIDP_UPSCALING_COEFFS :
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(upscale_factor >= FP_0_66667) ? MALIDP_DOWNSCALING_1_5_COEFFS :
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(upscale_factor >= FP_0_50000) ? MALIDP_DOWNSCALING_2_COEFFS :
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(upscale_factor >= FP_0_36363) ? MALIDP_DOWNSCALING_2_75_COEFFS :
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MALIDP_DOWNSCALING_4_COEFFS;
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}
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#undef FP_0_25000
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#undef FP_0_36363
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#undef FP_0_50000
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#undef FP_0_66667
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#undef FP_1_00000
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static inline void malidp_se_set_enh_coeffs(struct malidp_hw_device *hwdev)
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{
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static const s32 enhancer_coeffs[] = {
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-8, -8, -8, -8, 128, -8, -8, -8, -8
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};
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u32 val = MALIDP_SE_SET_ENH_LIMIT_LOW(MALIDP_SE_ENH_LOW_LEVEL) |
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MALIDP_SE_SET_ENH_LIMIT_HIGH(MALIDP_SE_ENH_HIGH_LEVEL);
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u32 image_enh = hwdev->hw->map.se_base +
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((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
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0x10 : 0xC) + MALIDP_SE_IMAGE_ENH;
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u32 enh_coeffs = image_enh + MALIDP_SE_ENH_COEFF0;
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int i;
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malidp_hw_write(hwdev, val, image_enh);
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for (i = 0; i < ARRAY_SIZE(enhancer_coeffs); ++i)
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malidp_hw_write(hwdev, enhancer_coeffs[i], enh_coeffs + i * 4);
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}
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/*
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* background color components are defined as 12bits values,
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* they will be shifted right when stored on hardware that
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* supports only 8bits per channel
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*/
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#define MALIDP_BGND_COLOR_R 0x000
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#define MALIDP_BGND_COLOR_G 0x000
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#define MALIDP_BGND_COLOR_B 0x000
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#define MALIDP_COLORADJ_NUM_COEFFS 12
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#define MALIDP_COEFFTAB_NUM_COEFFS 64
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#define MALIDP_GAMMA_LUT_SIZE 4096
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#define AFBC_SIZE_MASK AFBC_FORMAT_MOD_BLOCK_SIZE_MASK
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#define AFBC_SIZE_16X16 AFBC_FORMAT_MOD_BLOCK_SIZE_16x16
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#define AFBC_YTR AFBC_FORMAT_MOD_YTR
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#define AFBC_SPARSE AFBC_FORMAT_MOD_SPARSE
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#define AFBC_CBR AFBC_FORMAT_MOD_CBR
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#define AFBC_SPLIT AFBC_FORMAT_MOD_SPLIT
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#define AFBC_TILED AFBC_FORMAT_MOD_TILED
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#define AFBC_SC AFBC_FORMAT_MOD_SC
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#define AFBC_MOD_VALID_BITS (AFBC_SIZE_MASK | AFBC_YTR | AFBC_SPLIT | \
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AFBC_SPARSE | AFBC_CBR | AFBC_TILED | AFBC_SC)
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extern const u64 malidp_format_modifiers[];
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#endif /* __MALIDP_HW_H__ */
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