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![Danilo Krummrich](/assets/img/avatar_default.png)
Use drm managed resource allocation (drmm_universal_plane_alloc()) in order to get rid of the explicit destroy hook in struct drm_plane_funcs. Signed-off-by: Danilo Krummrich <dakr@redhat.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221026155934.125294-5-dakr@redhat.com
1033 lines
29 KiB
C
1033 lines
29 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
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* Author: Liviu Dudau <Liviu.Dudau@arm.com>
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*
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* ARM Mali DP plane manipulation routines.
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*/
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#include <linux/iommu.h>
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#include <linux/platform_device.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_blend.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_fb_dma_helper.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_framebuffer.h>
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#include <drm/drm_gem_dma_helper.h>
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#include <drm/drm_gem_framebuffer_helper.h>
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#include <drm/drm_print.h>
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#include "malidp_hw.h"
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#include "malidp_drv.h"
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/* Layer specific register offsets */
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#define MALIDP_LAYER_FORMAT 0x000
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#define LAYER_FORMAT_MASK 0x3f
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#define MALIDP_LAYER_CONTROL 0x004
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#define LAYER_ENABLE (1 << 0)
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#define LAYER_FLOWCFG_MASK 7
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#define LAYER_FLOWCFG(x) (((x) & LAYER_FLOWCFG_MASK) << 1)
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#define LAYER_FLOWCFG_SCALE_SE 3
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#define LAYER_ROT_OFFSET 8
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#define LAYER_H_FLIP (1 << 10)
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#define LAYER_V_FLIP (1 << 11)
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#define LAYER_ROT_MASK (0xf << 8)
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#define LAYER_COMP_MASK (0x3 << 12)
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#define LAYER_COMP_PIXEL (0x3 << 12)
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#define LAYER_COMP_PLANE (0x2 << 12)
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#define LAYER_PMUL_ENABLE (0x1 << 14)
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#define LAYER_ALPHA_OFFSET (16)
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#define LAYER_ALPHA_MASK (0xff)
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#define LAYER_ALPHA(x) (((x) & LAYER_ALPHA_MASK) << LAYER_ALPHA_OFFSET)
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#define MALIDP_LAYER_COMPOSE 0x008
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#define MALIDP_LAYER_SIZE 0x00c
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#define LAYER_H_VAL(x) (((x) & 0x1fff) << 0)
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#define LAYER_V_VAL(x) (((x) & 0x1fff) << 16)
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#define MALIDP_LAYER_COMP_SIZE 0x010
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#define MALIDP_LAYER_OFFSET 0x014
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#define MALIDP550_LS_ENABLE 0x01c
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#define MALIDP550_LS_R1_IN_SIZE 0x020
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#define MODIFIERS_COUNT_MAX 15
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/*
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* This 4-entry look-up-table is used to determine the full 8-bit alpha value
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* for formats with 1- or 2-bit alpha channels.
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* We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0%
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* opacity for 2-bit formats.
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*/
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#define MALIDP_ALPHA_LUT 0xffaa5500
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/* page sizes the MMU prefetcher can support */
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#define MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES (SZ_4K | SZ_64K)
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#define MALIDP_MMU_PREFETCH_FULL_PGSIZES (SZ_1M | SZ_2M)
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/* readahead for partial-frame prefetch */
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#define MALIDP_MMU_PREFETCH_READAHEAD 8
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/*
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* Replicate what the default ->reset hook does: free the state pointer and
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* allocate a new empty object. We just need enough space to store
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* a malidp_plane_state instead of a drm_plane_state.
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*/
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static void malidp_plane_reset(struct drm_plane *plane)
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{
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struct malidp_plane_state *state = to_malidp_plane_state(plane->state);
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if (state)
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__drm_atomic_helper_plane_destroy_state(&state->base);
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kfree(state);
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plane->state = NULL;
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state = kzalloc(sizeof(*state), GFP_KERNEL);
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if (state)
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__drm_atomic_helper_plane_reset(plane, &state->base);
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}
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static struct
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drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane)
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{
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struct malidp_plane_state *state, *m_state;
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if (!plane->state)
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return NULL;
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state = kmalloc(sizeof(*state), GFP_KERNEL);
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if (!state)
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return NULL;
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m_state = to_malidp_plane_state(plane->state);
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__drm_atomic_helper_plane_duplicate_state(plane, &state->base);
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state->rotmem_size = m_state->rotmem_size;
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state->format = m_state->format;
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state->n_planes = m_state->n_planes;
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state->mmu_prefetch_mode = m_state->mmu_prefetch_mode;
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state->mmu_prefetch_pgsize = m_state->mmu_prefetch_pgsize;
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return &state->base;
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}
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static void malidp_destroy_plane_state(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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struct malidp_plane_state *m_state = to_malidp_plane_state(state);
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__drm_atomic_helper_plane_destroy_state(state);
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kfree(m_state);
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}
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static const char * const prefetch_mode_names[] = {
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[MALIDP_PREFETCH_MODE_NONE] = "MMU_PREFETCH_NONE",
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[MALIDP_PREFETCH_MODE_PARTIAL] = "MMU_PREFETCH_PARTIAL",
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[MALIDP_PREFETCH_MODE_FULL] = "MMU_PREFETCH_FULL",
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};
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static void malidp_plane_atomic_print_state(struct drm_printer *p,
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const struct drm_plane_state *state)
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{
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struct malidp_plane_state *ms = to_malidp_plane_state(state);
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drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size);
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drm_printf(p, "\tformat_id=%u\n", ms->format);
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drm_printf(p, "\tn_planes=%u\n", ms->n_planes);
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drm_printf(p, "\tmmu_prefetch_mode=%s\n",
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prefetch_mode_names[ms->mmu_prefetch_mode]);
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drm_printf(p, "\tmmu_prefetch_pgsize=%d\n", ms->mmu_prefetch_pgsize);
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}
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bool malidp_format_mod_supported(struct drm_device *drm,
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u32 format, u64 modifier)
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{
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const struct drm_format_info *info;
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const u64 *modifiers;
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struct malidp_drm *malidp = drm_to_malidp(drm);
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const struct malidp_hw_regmap *map = &malidp->dev->hw->map;
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if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
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return false;
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/* Some pixel formats are supported without any modifier */
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if (modifier == DRM_FORMAT_MOD_LINEAR) {
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/*
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* However these pixel formats need to be supported with
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* modifiers only
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*/
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return !malidp_hw_format_is_afbc_only(format);
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}
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if (!fourcc_mod_is_vendor(modifier, ARM)) {
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DRM_ERROR("Unknown modifier (not Arm)\n");
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return false;
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}
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if (modifier &
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~DRM_FORMAT_MOD_ARM_AFBC(AFBC_MOD_VALID_BITS)) {
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DRM_DEBUG_KMS("Unsupported modifiers\n");
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return false;
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}
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modifiers = malidp_format_modifiers;
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/* SPLIT buffers must use SPARSE layout */
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if (WARN_ON_ONCE((modifier & AFBC_SPLIT) && !(modifier & AFBC_SPARSE)))
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return false;
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/* CBR only applies to YUV formats, where YTR should be always 0 */
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if (WARN_ON_ONCE((modifier & AFBC_CBR) && (modifier & AFBC_YTR)))
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return false;
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while (*modifiers != DRM_FORMAT_MOD_INVALID) {
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if (*modifiers == modifier)
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break;
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modifiers++;
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}
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/* return false, if the modifier was not found */
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if (*modifiers == DRM_FORMAT_MOD_INVALID) {
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DRM_DEBUG_KMS("Unsupported modifier\n");
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return false;
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}
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info = drm_format_info(format);
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if (info->num_planes != 1) {
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DRM_DEBUG_KMS("AFBC buffers expect one plane\n");
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return false;
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}
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if (malidp_hw_format_is_linear_only(format) == true) {
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DRM_DEBUG_KMS("Given format (0x%x) is supported is linear mode only\n",
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format);
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return false;
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}
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/*
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* RGB formats need to provide YTR modifier and YUV formats should not
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* provide YTR modifier.
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*/
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if (!(info->is_yuv) != !!(modifier & AFBC_FORMAT_MOD_YTR)) {
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DRM_DEBUG_KMS("AFBC_FORMAT_MOD_YTR is %s for %s formats\n",
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info->is_yuv ? "disallowed" : "mandatory",
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info->is_yuv ? "YUV" : "RGB");
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return false;
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}
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if (modifier & AFBC_SPLIT) {
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if (!info->is_yuv) {
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if (info->cpp[0] <= 2) {
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DRM_DEBUG_KMS("RGB formats <= 16bpp are not supported with SPLIT\n");
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return false;
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}
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}
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if ((info->hsub != 1) || (info->vsub != 1)) {
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if (!(format == DRM_FORMAT_YUV420_10BIT &&
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(map->features & MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT))) {
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DRM_DEBUG_KMS("Formats which are sub-sampled should never be split\n");
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return false;
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}
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}
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}
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if (modifier & AFBC_CBR) {
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if ((info->hsub == 1) || (info->vsub == 1)) {
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DRM_DEBUG_KMS("Formats which are not sub-sampled should not have CBR set\n");
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return false;
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}
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}
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return true;
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}
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static bool malidp_format_mod_supported_per_plane(struct drm_plane *plane,
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u32 format, u64 modifier)
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{
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return malidp_format_mod_supported(plane->dev, format, modifier);
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}
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static const struct drm_plane_funcs malidp_de_plane_funcs = {
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.update_plane = drm_atomic_helper_update_plane,
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.disable_plane = drm_atomic_helper_disable_plane,
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.reset = malidp_plane_reset,
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.atomic_duplicate_state = malidp_duplicate_plane_state,
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.atomic_destroy_state = malidp_destroy_plane_state,
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.atomic_print_state = malidp_plane_atomic_print_state,
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.format_mod_supported = malidp_format_mod_supported_per_plane,
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};
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static int malidp_se_check_scaling(struct malidp_plane *mp,
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struct drm_plane_state *state)
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{
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struct drm_crtc_state *crtc_state =
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drm_atomic_get_existing_crtc_state(state->state, state->crtc);
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struct malidp_crtc_state *mc;
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u32 src_w, src_h;
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int ret;
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if (!crtc_state)
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return -EINVAL;
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mc = to_malidp_crtc_state(crtc_state);
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ret = drm_atomic_helper_check_plane_state(state, crtc_state,
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0, INT_MAX, true, true);
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if (ret)
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return ret;
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if (state->rotation & MALIDP_ROTATED_MASK) {
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src_w = state->src_h >> 16;
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src_h = state->src_w >> 16;
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} else {
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src_w = state->src_w >> 16;
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src_h = state->src_h >> 16;
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}
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if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) {
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/* Scaling not necessary for this plane. */
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mc->scaled_planes_mask &= ~(mp->layer->id);
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return 0;
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}
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if (mp->layer->id & (DE_SMART | DE_GRAPHICS2))
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return -EINVAL;
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mc->scaled_planes_mask |= mp->layer->id;
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/* Defer scaling requirements calculation to the crtc check. */
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return 0;
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}
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static u32 malidp_get_pgsize_bitmap(struct malidp_plane *mp)
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{
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struct iommu_domain *mmu_dom;
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mmu_dom = iommu_get_domain_for_dev(mp->base.dev->dev);
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if (mmu_dom)
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return mmu_dom->pgsize_bitmap;
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return 0;
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}
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/*
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* Check if the framebuffer is entirely made up of pages at least pgsize in
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* size. Only a heuristic: assumes that each scatterlist entry has been aligned
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* to the largest page size smaller than its length and that the MMU maps to
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* the largest page size possible.
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*/
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static bool malidp_check_pages_threshold(struct malidp_plane_state *ms,
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u32 pgsize)
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{
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int i;
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for (i = 0; i < ms->n_planes; i++) {
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struct drm_gem_object *obj;
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struct drm_gem_dma_object *dma_obj;
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struct sg_table *sgt;
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struct scatterlist *sgl;
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obj = drm_gem_fb_get_obj(ms->base.fb, i);
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dma_obj = to_drm_gem_dma_obj(obj);
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if (dma_obj->sgt)
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sgt = dma_obj->sgt;
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else
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sgt = obj->funcs->get_sg_table(obj);
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if (IS_ERR(sgt))
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return false;
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sgl = sgt->sgl;
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while (sgl) {
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if (sgl->length < pgsize) {
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if (!dma_obj->sgt)
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kfree(sgt);
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return false;
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}
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sgl = sg_next(sgl);
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}
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if (!dma_obj->sgt)
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kfree(sgt);
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}
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return true;
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}
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/*
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* Check if it is possible to enable partial-frame MMU prefetch given the
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* current format, AFBC state and rotation.
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*/
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static bool malidp_partial_prefetch_supported(u32 format, u64 modifier,
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unsigned int rotation)
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{
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bool afbc, sparse;
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/* rotation and horizontal flip not supported for partial prefetch */
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if (rotation & (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 |
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DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X))
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return false;
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afbc = modifier & DRM_FORMAT_MOD_ARM_AFBC(0);
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sparse = modifier & AFBC_FORMAT_MOD_SPARSE;
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switch (format) {
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case DRM_FORMAT_ARGB2101010:
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case DRM_FORMAT_RGBA1010102:
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case DRM_FORMAT_BGRA1010102:
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_RGBA8888:
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case DRM_FORMAT_BGRA8888:
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_RGBX8888:
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case DRM_FORMAT_BGRX8888:
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case DRM_FORMAT_RGB888:
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case DRM_FORMAT_RGBA5551:
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case DRM_FORMAT_RGB565:
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/* always supported */
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return true;
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case DRM_FORMAT_ABGR2101010:
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case DRM_FORMAT_ABGR8888:
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case DRM_FORMAT_ABGR1555:
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case DRM_FORMAT_BGR565:
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/* supported, but if AFBC then must be sparse mode */
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return (!afbc) || (afbc && sparse);
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case DRM_FORMAT_BGR888:
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/* supported, but not for AFBC */
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return !afbc;
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case DRM_FORMAT_YUYV:
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case DRM_FORMAT_UYVY:
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case DRM_FORMAT_NV12:
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case DRM_FORMAT_YUV420:
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/* not supported */
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return false;
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default:
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return false;
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}
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}
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/*
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* Select the preferred MMU prefetch mode. Full-frame prefetch is preferred as
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* long as the framebuffer is all large pages. Otherwise partial-frame prefetch
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* is selected as long as it is supported for the current format. The selected
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* page size for prefetch is returned in pgsize_bitmap.
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*/
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static enum mmu_prefetch_mode malidp_mmu_prefetch_select_mode
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(struct malidp_plane_state *ms, u32 *pgsize_bitmap)
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{
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u32 pgsizes;
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/* get the full-frame prefetch page size(s) supported by the MMU */
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pgsizes = *pgsize_bitmap & MALIDP_MMU_PREFETCH_FULL_PGSIZES;
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while (pgsizes) {
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u32 largest_pgsize = 1 << __fls(pgsizes);
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if (malidp_check_pages_threshold(ms, largest_pgsize)) {
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*pgsize_bitmap = largest_pgsize;
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return MALIDP_PREFETCH_MODE_FULL;
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}
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pgsizes -= largest_pgsize;
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}
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/* get the partial-frame prefetch page size(s) supported by the MMU */
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pgsizes = *pgsize_bitmap & MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES;
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if (malidp_partial_prefetch_supported(ms->base.fb->format->format,
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ms->base.fb->modifier,
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ms->base.rotation)) {
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/* partial prefetch using the smallest page size */
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*pgsize_bitmap = 1 << __ffs(pgsizes);
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return MALIDP_PREFETCH_MODE_PARTIAL;
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}
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*pgsize_bitmap = 0;
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return MALIDP_PREFETCH_MODE_NONE;
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}
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static u32 malidp_calc_mmu_control_value(enum mmu_prefetch_mode mode,
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u8 readahead, u8 n_planes, u32 pgsize)
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{
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u32 mmu_ctrl = 0;
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if (mode != MALIDP_PREFETCH_MODE_NONE) {
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mmu_ctrl |= MALIDP_MMU_CTRL_EN;
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if (mode == MALIDP_PREFETCH_MODE_PARTIAL) {
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mmu_ctrl |= MALIDP_MMU_CTRL_MODE;
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mmu_ctrl |= MALIDP_MMU_CTRL_PP_NUM_REQ(readahead);
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}
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if (pgsize == SZ_64K || pgsize == SZ_2M) {
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|
int i;
|
|
|
|
for (i = 0; i < n_planes; i++)
|
|
mmu_ctrl |= MALIDP_MMU_CTRL_PX_PS(i);
|
|
}
|
|
}
|
|
|
|
return mmu_ctrl;
|
|
}
|
|
|
|
static void malidp_de_prefetch_settings(struct malidp_plane *mp,
|
|
struct malidp_plane_state *ms)
|
|
{
|
|
if (!mp->layer->mmu_ctrl_offset)
|
|
return;
|
|
|
|
/* get the page sizes supported by the MMU */
|
|
ms->mmu_prefetch_pgsize = malidp_get_pgsize_bitmap(mp);
|
|
ms->mmu_prefetch_mode =
|
|
malidp_mmu_prefetch_select_mode(ms, &ms->mmu_prefetch_pgsize);
|
|
}
|
|
|
|
static int malidp_de_plane_check(struct drm_plane *plane,
|
|
struct drm_atomic_state *state)
|
|
{
|
|
struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
|
|
plane);
|
|
struct malidp_plane *mp = to_malidp_plane(plane);
|
|
struct malidp_plane_state *ms = to_malidp_plane_state(new_plane_state);
|
|
bool rotated = new_plane_state->rotation & MALIDP_ROTATED_MASK;
|
|
struct drm_framebuffer *fb;
|
|
u16 pixel_alpha = new_plane_state->pixel_blend_mode;
|
|
int i, ret;
|
|
unsigned int block_w, block_h;
|
|
|
|
if (!new_plane_state->crtc || WARN_ON(!new_plane_state->fb))
|
|
return 0;
|
|
|
|
fb = new_plane_state->fb;
|
|
|
|
ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map,
|
|
mp->layer->id, fb->format->format,
|
|
!!fb->modifier);
|
|
if (ms->format == MALIDP_INVALID_FORMAT_ID)
|
|
return -EINVAL;
|
|
|
|
ms->n_planes = fb->format->num_planes;
|
|
for (i = 0; i < ms->n_planes; i++) {
|
|
u8 alignment = malidp_hw_get_pitch_align(mp->hwdev, rotated);
|
|
|
|
if (((fb->pitches[i] * drm_format_info_block_height(fb->format, i))
|
|
& (alignment - 1)) && !(fb->modifier)) {
|
|
DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n",
|
|
fb->pitches[i], i);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
block_w = drm_format_info_block_width(fb->format, 0);
|
|
block_h = drm_format_info_block_height(fb->format, 0);
|
|
if (fb->width % block_w || fb->height % block_h) {
|
|
DRM_DEBUG_KMS("Buffer width/height needs to be a multiple of tile sizes");
|
|
return -EINVAL;
|
|
}
|
|
if ((new_plane_state->src_x >> 16) % block_w || (new_plane_state->src_y >> 16) % block_h) {
|
|
DRM_DEBUG_KMS("Plane src_x/src_y needs to be a multiple of tile sizes");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if ((new_plane_state->crtc_w > mp->hwdev->max_line_size) ||
|
|
(new_plane_state->crtc_h > mp->hwdev->max_line_size) ||
|
|
(new_plane_state->crtc_w < mp->hwdev->min_line_size) ||
|
|
(new_plane_state->crtc_h < mp->hwdev->min_line_size))
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* DP550/650 video layers can accept 3 plane formats only if
|
|
* fb->pitches[1] == fb->pitches[2] since they don't have a
|
|
* third plane stride register.
|
|
*/
|
|
if (ms->n_planes == 3 &&
|
|
!(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) &&
|
|
(new_plane_state->fb->pitches[1] != new_plane_state->fb->pitches[2]))
|
|
return -EINVAL;
|
|
|
|
ret = malidp_se_check_scaling(mp, new_plane_state);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* validate the rotation constraints for each layer */
|
|
if (new_plane_state->rotation != DRM_MODE_ROTATE_0) {
|
|
if (mp->layer->rot == ROTATE_NONE)
|
|
return -EINVAL;
|
|
if ((mp->layer->rot == ROTATE_COMPRESSED) && !(fb->modifier))
|
|
return -EINVAL;
|
|
/*
|
|
* packed RGB888 / BGR888 can't be rotated or flipped
|
|
* unless they are stored in a compressed way
|
|
*/
|
|
if ((fb->format->format == DRM_FORMAT_RGB888 ||
|
|
fb->format->format == DRM_FORMAT_BGR888) && !(fb->modifier))
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* SMART layer does not support AFBC */
|
|
if (mp->layer->id == DE_SMART && fb->modifier) {
|
|
DRM_ERROR("AFBC framebuffer not supported in SMART layer");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ms->rotmem_size = 0;
|
|
if (new_plane_state->rotation & MALIDP_ROTATED_MASK) {
|
|
int val;
|
|
|
|
val = mp->hwdev->hw->rotmem_required(mp->hwdev, new_plane_state->crtc_w,
|
|
new_plane_state->crtc_h,
|
|
fb->format->format,
|
|
!!(fb->modifier));
|
|
if (val < 0)
|
|
return val;
|
|
|
|
ms->rotmem_size = val;
|
|
}
|
|
|
|
/* HW can't support plane + pixel blending */
|
|
if ((new_plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE) &&
|
|
(pixel_alpha != DRM_MODE_BLEND_PIXEL_NONE) &&
|
|
fb->format->has_alpha)
|
|
return -EINVAL;
|
|
|
|
malidp_de_prefetch_settings(mp, ms);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void malidp_de_set_plane_pitches(struct malidp_plane *mp,
|
|
int num_planes, unsigned int pitches[3])
|
|
{
|
|
int i;
|
|
int num_strides = num_planes;
|
|
|
|
if (!mp->layer->stride_offset)
|
|
return;
|
|
|
|
if (num_planes == 3)
|
|
num_strides = (mp->hwdev->hw->features &
|
|
MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2;
|
|
|
|
/*
|
|
* The drm convention for pitch is that it needs to cover width * cpp,
|
|
* but our hardware wants the pitch/stride to cover all rows included
|
|
* in a tile.
|
|
*/
|
|
for (i = 0; i < num_strides; ++i) {
|
|
unsigned int block_h = drm_format_info_block_height(mp->base.state->fb->format, i);
|
|
|
|
malidp_hw_write(mp->hwdev, pitches[i] * block_h,
|
|
mp->layer->base +
|
|
mp->layer->stride_offset + i * 4);
|
|
}
|
|
}
|
|
|
|
static const s16
|
|
malidp_yuv2rgb_coeffs[][DRM_COLOR_RANGE_MAX][MALIDP_COLORADJ_NUM_COEFFS] = {
|
|
[DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
|
|
1192, 0, 1634,
|
|
1192, -401, -832,
|
|
1192, 2066, 0,
|
|
64, 512, 512
|
|
},
|
|
[DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = {
|
|
1024, 0, 1436,
|
|
1024, -352, -731,
|
|
1024, 1815, 0,
|
|
0, 512, 512
|
|
},
|
|
[DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
|
|
1192, 0, 1836,
|
|
1192, -218, -546,
|
|
1192, 2163, 0,
|
|
64, 512, 512
|
|
},
|
|
[DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = {
|
|
1024, 0, 1613,
|
|
1024, -192, -479,
|
|
1024, 1900, 0,
|
|
0, 512, 512
|
|
},
|
|
[DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
|
|
1024, 0, 1476,
|
|
1024, -165, -572,
|
|
1024, 1884, 0,
|
|
0, 512, 512
|
|
},
|
|
[DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_FULL_RANGE] = {
|
|
1024, 0, 1510,
|
|
1024, -168, -585,
|
|
1024, 1927, 0,
|
|
0, 512, 512
|
|
}
|
|
};
|
|
|
|
static void malidp_de_set_color_encoding(struct malidp_plane *plane,
|
|
enum drm_color_encoding enc,
|
|
enum drm_color_range range)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; i++) {
|
|
/* coefficients are signed, two's complement values */
|
|
malidp_hw_write(plane->hwdev, malidp_yuv2rgb_coeffs[enc][range][i],
|
|
plane->layer->base + plane->layer->yuv2rgb_offset +
|
|
i * 4);
|
|
}
|
|
}
|
|
|
|
static void malidp_de_set_mmu_control(struct malidp_plane *mp,
|
|
struct malidp_plane_state *ms)
|
|
{
|
|
u32 mmu_ctrl;
|
|
|
|
/* check hardware supports MMU prefetch */
|
|
if (!mp->layer->mmu_ctrl_offset)
|
|
return;
|
|
|
|
mmu_ctrl = malidp_calc_mmu_control_value(ms->mmu_prefetch_mode,
|
|
MALIDP_MMU_PREFETCH_READAHEAD,
|
|
ms->n_planes,
|
|
ms->mmu_prefetch_pgsize);
|
|
|
|
malidp_hw_write(mp->hwdev, mmu_ctrl,
|
|
mp->layer->base + mp->layer->mmu_ctrl_offset);
|
|
}
|
|
|
|
static void malidp_set_plane_base_addr(struct drm_framebuffer *fb,
|
|
struct malidp_plane *mp,
|
|
int plane_index)
|
|
{
|
|
dma_addr_t dma_addr;
|
|
u16 ptr;
|
|
struct drm_plane *plane = &mp->base;
|
|
bool afbc = fb->modifier ? true : false;
|
|
|
|
ptr = mp->layer->ptr + (plane_index << 4);
|
|
|
|
/*
|
|
* drm_fb_dma_get_gem_addr() alters the physical base address of the
|
|
* framebuffer as per the plane's src_x, src_y co-ordinates (ie to
|
|
* take care of source cropping).
|
|
* For AFBC, this is not needed as the cropping is handled by _AD_CROP_H
|
|
* and _AD_CROP_V registers.
|
|
*/
|
|
if (!afbc) {
|
|
dma_addr = drm_fb_dma_get_gem_addr(fb, plane->state,
|
|
plane_index);
|
|
} else {
|
|
struct drm_gem_dma_object *obj;
|
|
|
|
obj = drm_fb_dma_get_gem_obj(fb, plane_index);
|
|
|
|
if (WARN_ON(!obj))
|
|
return;
|
|
dma_addr = obj->dma_addr;
|
|
}
|
|
|
|
malidp_hw_write(mp->hwdev, lower_32_bits(dma_addr), ptr);
|
|
malidp_hw_write(mp->hwdev, upper_32_bits(dma_addr), ptr + 4);
|
|
}
|
|
|
|
static void malidp_de_set_plane_afbc(struct drm_plane *plane)
|
|
{
|
|
struct malidp_plane *mp;
|
|
u32 src_w, src_h, val = 0, src_x, src_y;
|
|
struct drm_framebuffer *fb = plane->state->fb;
|
|
|
|
mp = to_malidp_plane(plane);
|
|
|
|
/* no afbc_decoder_offset means AFBC is not supported on this plane */
|
|
if (!mp->layer->afbc_decoder_offset)
|
|
return;
|
|
|
|
if (!fb->modifier) {
|
|
malidp_hw_write(mp->hwdev, 0, mp->layer->afbc_decoder_offset);
|
|
return;
|
|
}
|
|
|
|
/* convert src values from Q16 fixed point to integer */
|
|
src_w = plane->state->src_w >> 16;
|
|
src_h = plane->state->src_h >> 16;
|
|
src_x = plane->state->src_x >> 16;
|
|
src_y = plane->state->src_y >> 16;
|
|
|
|
val = ((fb->width - (src_x + src_w)) << MALIDP_AD_CROP_RIGHT_OFFSET) |
|
|
src_x;
|
|
malidp_hw_write(mp->hwdev, val,
|
|
mp->layer->afbc_decoder_offset + MALIDP_AD_CROP_H);
|
|
|
|
val = ((fb->height - (src_y + src_h)) << MALIDP_AD_CROP_BOTTOM_OFFSET) |
|
|
src_y;
|
|
malidp_hw_write(mp->hwdev, val,
|
|
mp->layer->afbc_decoder_offset + MALIDP_AD_CROP_V);
|
|
|
|
val = MALIDP_AD_EN;
|
|
if (fb->modifier & AFBC_FORMAT_MOD_SPLIT)
|
|
val |= MALIDP_AD_BS;
|
|
if (fb->modifier & AFBC_FORMAT_MOD_YTR)
|
|
val |= MALIDP_AD_YTR;
|
|
|
|
malidp_hw_write(mp->hwdev, val, mp->layer->afbc_decoder_offset);
|
|
}
|
|
|
|
static void malidp_de_plane_update(struct drm_plane *plane,
|
|
struct drm_atomic_state *state)
|
|
{
|
|
struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
|
|
plane);
|
|
struct malidp_plane *mp;
|
|
struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);
|
|
struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
|
|
plane);
|
|
u16 pixel_alpha = new_state->pixel_blend_mode;
|
|
u8 plane_alpha = new_state->alpha >> 8;
|
|
u32 src_w, src_h, dest_w, dest_h, val;
|
|
int i;
|
|
struct drm_framebuffer *fb = plane->state->fb;
|
|
|
|
mp = to_malidp_plane(plane);
|
|
|
|
/*
|
|
* For AFBC framebuffer, use the framebuffer width and height for
|
|
* configuring layer input size register.
|
|
*/
|
|
if (fb->modifier) {
|
|
src_w = fb->width;
|
|
src_h = fb->height;
|
|
} else {
|
|
/* convert src values from Q16 fixed point to integer */
|
|
src_w = new_state->src_w >> 16;
|
|
src_h = new_state->src_h >> 16;
|
|
}
|
|
|
|
dest_w = new_state->crtc_w;
|
|
dest_h = new_state->crtc_h;
|
|
|
|
val = malidp_hw_read(mp->hwdev, mp->layer->base);
|
|
val = (val & ~LAYER_FORMAT_MASK) | ms->format;
|
|
malidp_hw_write(mp->hwdev, val, mp->layer->base);
|
|
|
|
for (i = 0; i < ms->n_planes; i++)
|
|
malidp_set_plane_base_addr(fb, mp, i);
|
|
|
|
malidp_de_set_mmu_control(mp, ms);
|
|
|
|
malidp_de_set_plane_pitches(mp, ms->n_planes,
|
|
new_state->fb->pitches);
|
|
|
|
if ((plane->state->color_encoding != old_state->color_encoding) ||
|
|
(plane->state->color_range != old_state->color_range))
|
|
malidp_de_set_color_encoding(mp, plane->state->color_encoding,
|
|
plane->state->color_range);
|
|
|
|
malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
|
|
mp->layer->base + MALIDP_LAYER_SIZE);
|
|
|
|
malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h),
|
|
mp->layer->base + MALIDP_LAYER_COMP_SIZE);
|
|
|
|
malidp_hw_write(mp->hwdev, LAYER_H_VAL(new_state->crtc_x) |
|
|
LAYER_V_VAL(new_state->crtc_y),
|
|
mp->layer->base + MALIDP_LAYER_OFFSET);
|
|
|
|
if (mp->layer->id == DE_SMART) {
|
|
/*
|
|
* Enable the first rectangle in the SMART layer to be
|
|
* able to use it as a drm plane.
|
|
*/
|
|
malidp_hw_write(mp->hwdev, 1,
|
|
mp->layer->base + MALIDP550_LS_ENABLE);
|
|
malidp_hw_write(mp->hwdev,
|
|
LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
|
|
mp->layer->base + MALIDP550_LS_R1_IN_SIZE);
|
|
}
|
|
|
|
malidp_de_set_plane_afbc(plane);
|
|
|
|
/* first clear the rotation bits */
|
|
val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL);
|
|
val &= ~LAYER_ROT_MASK;
|
|
|
|
/* setup the rotation and axis flip bits */
|
|
if (new_state->rotation & DRM_MODE_ROTATE_MASK)
|
|
val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) <<
|
|
LAYER_ROT_OFFSET;
|
|
if (new_state->rotation & DRM_MODE_REFLECT_X)
|
|
val |= LAYER_H_FLIP;
|
|
if (new_state->rotation & DRM_MODE_REFLECT_Y)
|
|
val |= LAYER_V_FLIP;
|
|
|
|
val &= ~(LAYER_COMP_MASK | LAYER_PMUL_ENABLE | LAYER_ALPHA(0xff));
|
|
|
|
if (new_state->alpha != DRM_BLEND_ALPHA_OPAQUE) {
|
|
val |= LAYER_COMP_PLANE;
|
|
} else if (new_state->fb->format->has_alpha) {
|
|
/* We only care about blend mode if the format has alpha */
|
|
switch (pixel_alpha) {
|
|
case DRM_MODE_BLEND_PREMULTI:
|
|
val |= LAYER_COMP_PIXEL | LAYER_PMUL_ENABLE;
|
|
break;
|
|
case DRM_MODE_BLEND_COVERAGE:
|
|
val |= LAYER_COMP_PIXEL;
|
|
break;
|
|
}
|
|
}
|
|
val |= LAYER_ALPHA(plane_alpha);
|
|
|
|
val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK);
|
|
if (new_state->crtc) {
|
|
struct malidp_crtc_state *m =
|
|
to_malidp_crtc_state(new_state->crtc->state);
|
|
|
|
if (m->scaler_config.scale_enable &&
|
|
m->scaler_config.plane_src_id == mp->layer->id)
|
|
val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE);
|
|
}
|
|
|
|
/* set the 'enable layer' bit */
|
|
val |= LAYER_ENABLE;
|
|
|
|
malidp_hw_write(mp->hwdev, val,
|
|
mp->layer->base + MALIDP_LAYER_CONTROL);
|
|
}
|
|
|
|
static void malidp_de_plane_disable(struct drm_plane *plane,
|
|
struct drm_atomic_state *state)
|
|
{
|
|
struct malidp_plane *mp = to_malidp_plane(plane);
|
|
|
|
malidp_hw_clearbits(mp->hwdev,
|
|
LAYER_ENABLE | LAYER_FLOWCFG(LAYER_FLOWCFG_MASK),
|
|
mp->layer->base + MALIDP_LAYER_CONTROL);
|
|
}
|
|
|
|
static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = {
|
|
.atomic_check = malidp_de_plane_check,
|
|
.atomic_update = malidp_de_plane_update,
|
|
.atomic_disable = malidp_de_plane_disable,
|
|
};
|
|
|
|
static const uint64_t linear_only_modifiers[] = {
|
|
DRM_FORMAT_MOD_LINEAR,
|
|
DRM_FORMAT_MOD_INVALID
|
|
};
|
|
|
|
int malidp_de_planes_init(struct drm_device *drm)
|
|
{
|
|
struct malidp_drm *malidp = drm_to_malidp(drm);
|
|
const struct malidp_hw_regmap *map = &malidp->dev->hw->map;
|
|
struct malidp_plane *plane = NULL;
|
|
enum drm_plane_type plane_type;
|
|
unsigned long crtcs = BIT(drm->mode_config.num_crtc);
|
|
unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 |
|
|
DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
|
|
unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
|
|
BIT(DRM_MODE_BLEND_PREMULTI) |
|
|
BIT(DRM_MODE_BLEND_COVERAGE);
|
|
u32 *formats;
|
|
int ret, i = 0, j = 0, n;
|
|
u64 supported_modifiers[MODIFIERS_COUNT_MAX];
|
|
const u64 *modifiers;
|
|
|
|
modifiers = malidp_format_modifiers;
|
|
|
|
if (!(map->features & MALIDP_DEVICE_AFBC_SUPPORT_SPLIT)) {
|
|
/*
|
|
* Since our hardware does not support SPLIT, so build the list
|
|
* of supported modifiers excluding SPLIT ones.
|
|
*/
|
|
while (*modifiers != DRM_FORMAT_MOD_INVALID) {
|
|
if (!(*modifiers & AFBC_SPLIT))
|
|
supported_modifiers[j++] = *modifiers;
|
|
|
|
modifiers++;
|
|
}
|
|
supported_modifiers[j++] = DRM_FORMAT_MOD_INVALID;
|
|
modifiers = supported_modifiers;
|
|
}
|
|
|
|
formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL);
|
|
if (!formats) {
|
|
ret = -ENOMEM;
|
|
goto cleanup;
|
|
}
|
|
|
|
for (i = 0; i < map->n_layers; i++) {
|
|
u8 id = map->layers[i].id;
|
|
|
|
/* build the list of DRM supported formats based on the map */
|
|
for (n = 0, j = 0; j < map->n_pixel_formats; j++) {
|
|
if ((map->pixel_formats[j].layer & id) == id)
|
|
formats[n++] = map->pixel_formats[j].format;
|
|
}
|
|
|
|
plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
|
|
DRM_PLANE_TYPE_OVERLAY;
|
|
|
|
/*
|
|
* All the layers except smart layer supports AFBC modifiers.
|
|
*/
|
|
plane = drmm_universal_plane_alloc(drm, struct malidp_plane, base,
|
|
crtcs, &malidp_de_plane_funcs, formats, n,
|
|
(id == DE_SMART) ? linear_only_modifiers :
|
|
modifiers, plane_type, NULL);
|
|
if (IS_ERR(plane)) {
|
|
ret = PTR_ERR(plane);
|
|
goto cleanup;
|
|
}
|
|
|
|
drm_plane_helper_add(&plane->base,
|
|
&malidp_de_plane_helper_funcs);
|
|
plane->hwdev = malidp->dev;
|
|
plane->layer = &map->layers[i];
|
|
|
|
drm_plane_create_alpha_property(&plane->base);
|
|
drm_plane_create_blend_mode_property(&plane->base, blend_caps);
|
|
|
|
if (id == DE_SMART) {
|
|
/* Skip the features which the SMART layer doesn't have. */
|
|
continue;
|
|
}
|
|
|
|
drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags);
|
|
malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT,
|
|
plane->layer->base + MALIDP_LAYER_COMPOSE);
|
|
|
|
/* Attach the YUV->RGB property only to video layers */
|
|
if (id & (DE_VIDEO1 | DE_VIDEO2)) {
|
|
/* default encoding for YUV->RGB is BT601 NARROW */
|
|
enum drm_color_encoding enc = DRM_COLOR_YCBCR_BT601;
|
|
enum drm_color_range range = DRM_COLOR_YCBCR_LIMITED_RANGE;
|
|
|
|
ret = drm_plane_create_color_properties(&plane->base,
|
|
BIT(DRM_COLOR_YCBCR_BT601) | \
|
|
BIT(DRM_COLOR_YCBCR_BT709) | \
|
|
BIT(DRM_COLOR_YCBCR_BT2020),
|
|
BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | \
|
|
BIT(DRM_COLOR_YCBCR_FULL_RANGE),
|
|
enc, range);
|
|
if (!ret)
|
|
/* program the HW registers */
|
|
malidp_de_set_color_encoding(plane, enc, range);
|
|
else
|
|
DRM_WARN("Failed to create video layer %d color properties\n", id);
|
|
}
|
|
}
|
|
|
|
kfree(formats);
|
|
|
|
return 0;
|
|
|
|
cleanup:
|
|
kfree(formats);
|
|
|
|
return ret;
|
|
}
|