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![Zack Rusin](/assets/img/avatar_default.png)
The fb_base in struct drm_mode_config has been unused for a long time. Some drivers set it and some don't leading to a very confusing state where the variable can't be relied upon, because there's no indication as to which driver sets it and which doesn't. The only usage of fb_base is internal to two drivers so instead of trying to force it into all the drivers to get it into a coherent state completely remove it. Signed-off-by: Zack Rusin <zackr@vmware.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Thomas Zimmermann <tzimemrmann@suse.de> Acked-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221019024401.394617-1-zack@kde.org
831 lines
22 KiB
C
831 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2010 Matt Turner.
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* Copyright 2012 Red Hat
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*
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* Authors: Matthew Garrett
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* Matt Turner
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* Dave Airlie
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*/
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#include <linux/delay.h>
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#include <linux/iosys-map.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_damage_helper.h>
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#include <drm/drm_format_helper.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_framebuffer.h>
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#include <drm/drm_gem_atomic_helper.h>
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#include <drm/drm_gem_framebuffer_helper.h>
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#include <drm/drm_print.h>
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#include <drm/drm_probe_helper.h>
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#include "mgag200_drv.h"
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/*
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* This file contains setup code for the CRTC.
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*/
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static void mgag200_crtc_set_gamma_linear(struct mga_device *mdev,
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const struct drm_format_info *format)
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{
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int i;
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WREG8(DAC_INDEX + MGA1064_INDEX, 0);
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switch (format->format) {
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case DRM_FORMAT_RGB565:
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/* Use better interpolation, to take 32 values from 0 to 255 */
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for (i = 0; i < MGAG200_LUT_SIZE / 8; i++) {
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WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4);
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WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16);
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WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4);
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}
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/* Green has one more bit, so add padding with 0 for red and blue. */
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for (i = MGAG200_LUT_SIZE / 8; i < MGAG200_LUT_SIZE / 4; i++) {
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WREG8(DAC_INDEX + MGA1064_COL_PAL, 0);
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WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16);
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WREG8(DAC_INDEX + MGA1064_COL_PAL, 0);
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}
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break;
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case DRM_FORMAT_RGB888:
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case DRM_FORMAT_XRGB8888:
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for (i = 0; i < MGAG200_LUT_SIZE; i++) {
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WREG8(DAC_INDEX + MGA1064_COL_PAL, i);
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WREG8(DAC_INDEX + MGA1064_COL_PAL, i);
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WREG8(DAC_INDEX + MGA1064_COL_PAL, i);
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}
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break;
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default:
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drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n",
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&format->format);
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break;
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}
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}
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static void mgag200_crtc_set_gamma(struct mga_device *mdev,
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const struct drm_format_info *format,
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struct drm_color_lut *lut)
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{
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int i;
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WREG8(DAC_INDEX + MGA1064_INDEX, 0);
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switch (format->format) {
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case DRM_FORMAT_RGB565:
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/* Use better interpolation, to take 32 values from lut[0] to lut[255] */
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for (i = 0; i < MGAG200_LUT_SIZE / 8; i++) {
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WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].red >> 8);
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WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8);
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WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].blue >> 8);
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}
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/* Green has one more bit, so add padding with 0 for red and blue. */
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for (i = MGAG200_LUT_SIZE / 8; i < MGAG200_LUT_SIZE / 4; i++) {
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WREG8(DAC_INDEX + MGA1064_COL_PAL, 0);
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WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8);
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WREG8(DAC_INDEX + MGA1064_COL_PAL, 0);
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}
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break;
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case DRM_FORMAT_RGB888:
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case DRM_FORMAT_XRGB8888:
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for (i = 0; i < MGAG200_LUT_SIZE; i++) {
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WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].red >> 8);
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WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].green >> 8);
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WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].blue >> 8);
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}
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break;
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default:
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drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n",
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&format->format);
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break;
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}
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}
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static inline void mga_wait_vsync(struct mga_device *mdev)
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{
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unsigned long timeout = jiffies + HZ/10;
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unsigned int status = 0;
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do {
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status = RREG32(MGAREG_Status);
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} while ((status & 0x08) && time_before(jiffies, timeout));
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timeout = jiffies + HZ/10;
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status = 0;
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do {
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status = RREG32(MGAREG_Status);
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} while (!(status & 0x08) && time_before(jiffies, timeout));
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}
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static inline void mga_wait_busy(struct mga_device *mdev)
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{
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unsigned long timeout = jiffies + HZ;
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unsigned int status = 0;
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do {
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status = RREG8(MGAREG_Status + 2);
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} while ((status & 0x01) && time_before(jiffies, timeout));
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}
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/*
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* This is how the framebuffer base address is stored in g200 cards:
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* * Assume @offset is the gpu_addr variable of the framebuffer object
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* * Then addr is the number of _pixels_ (not bytes) from the start of
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* VRAM to the first pixel we want to display. (divided by 2 for 32bit
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* framebuffers)
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* * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
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* addr<20> -> CRTCEXT0<6>
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* addr<19-16> -> CRTCEXT0<3-0>
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* addr<15-8> -> CRTCC<7-0>
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* addr<7-0> -> CRTCD<7-0>
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*
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* CRTCEXT0 has to be programmed last to trigger an update and make the
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* new addr variable take effect.
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*/
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static void mgag200_set_startadd(struct mga_device *mdev,
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unsigned long offset)
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{
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struct drm_device *dev = &mdev->base;
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u32 startadd;
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u8 crtcc, crtcd, crtcext0;
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startadd = offset / 8;
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if (startadd > 0)
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drm_WARN_ON_ONCE(dev, mdev->info->bug_no_startadd);
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/*
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* Can't store addresses any higher than that, but we also
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* don't have more than 16 MiB of memory, so it should be fine.
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*/
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drm_WARN_ON(dev, startadd > 0x1fffff);
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RREG_ECRT(0x00, crtcext0);
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crtcc = (startadd >> 8) & 0xff;
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crtcd = startadd & 0xff;
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crtcext0 &= 0xb0;
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crtcext0 |= ((startadd >> 14) & BIT(6)) |
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((startadd >> 16) & 0x0f);
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WREG_CRT(0x0c, crtcc);
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WREG_CRT(0x0d, crtcd);
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WREG_ECRT(0x00, crtcext0);
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}
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void mgag200_init_registers(struct mga_device *mdev)
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{
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u8 crtc11, misc;
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WREG_SEQ(2, 0x0f);
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WREG_SEQ(3, 0x00);
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WREG_SEQ(4, 0x0e);
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WREG_CRT(10, 0);
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WREG_CRT(11, 0);
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WREG_CRT(12, 0);
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WREG_CRT(13, 0);
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WREG_CRT(14, 0);
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WREG_CRT(15, 0);
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RREG_CRT(0x11, crtc11);
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crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT |
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MGAREG_CRTC11_VINTEN |
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MGAREG_CRTC11_VINTCLR);
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WREG_CRT(0x11, crtc11);
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misc = RREG8(MGA_MISC_IN);
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misc |= MGAREG_MISC_IOADSEL;
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WREG8(MGA_MISC_OUT, misc);
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}
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void mgag200_set_mode_regs(struct mga_device *mdev, const struct drm_display_mode *mode)
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{
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const struct mgag200_device_info *info = mdev->info;
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unsigned int hdisplay, hsyncstart, hsyncend, htotal;
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unsigned int vdisplay, vsyncstart, vsyncend, vtotal;
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u8 misc, crtcext1, crtcext2, crtcext5;
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hdisplay = mode->hdisplay / 8 - 1;
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hsyncstart = mode->hsync_start / 8 - 1;
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hsyncend = mode->hsync_end / 8 - 1;
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htotal = mode->htotal / 8 - 1;
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/* Work around hardware quirk */
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if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
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htotal++;
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vdisplay = mode->vdisplay - 1;
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vsyncstart = mode->vsync_start - 1;
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vsyncend = mode->vsync_end - 1;
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vtotal = mode->vtotal - 2;
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misc = RREG8(MGA_MISC_IN);
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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misc |= MGAREG_MISC_HSYNCPOL;
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else
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misc &= ~MGAREG_MISC_HSYNCPOL;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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misc |= MGAREG_MISC_VSYNCPOL;
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else
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misc &= ~MGAREG_MISC_VSYNCPOL;
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crtcext1 = (((htotal - 4) & 0x100) >> 8) |
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((hdisplay & 0x100) >> 7) |
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((hsyncstart & 0x100) >> 6) |
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(htotal & 0x40);
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if (info->has_vidrst)
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crtcext1 |= MGAREG_CRTCEXT1_VRSTEN |
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MGAREG_CRTCEXT1_HRSTEN;
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crtcext2 = ((vtotal & 0xc00) >> 10) |
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((vdisplay & 0x400) >> 8) |
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((vdisplay & 0xc00) >> 7) |
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((vsyncstart & 0xc00) >> 5) |
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((vdisplay & 0x400) >> 3);
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crtcext5 = 0x00;
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WREG_CRT(0, htotal - 4);
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WREG_CRT(1, hdisplay);
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WREG_CRT(2, hdisplay);
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WREG_CRT(3, (htotal & 0x1F) | 0x80);
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WREG_CRT(4, hsyncstart);
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WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
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WREG_CRT(6, vtotal & 0xFF);
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WREG_CRT(7, ((vtotal & 0x100) >> 8) |
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((vdisplay & 0x100) >> 7) |
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((vsyncstart & 0x100) >> 6) |
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((vdisplay & 0x100) >> 5) |
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((vdisplay & 0x100) >> 4) | /* linecomp */
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((vtotal & 0x200) >> 4) |
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((vdisplay & 0x200) >> 3) |
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((vsyncstart & 0x200) >> 2));
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WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
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((vdisplay & 0x200) >> 3));
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WREG_CRT(16, vsyncstart & 0xFF);
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WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
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WREG_CRT(18, vdisplay & 0xFF);
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WREG_CRT(20, 0);
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WREG_CRT(21, vdisplay & 0xFF);
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WREG_CRT(22, (vtotal + 1) & 0xFF);
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WREG_CRT(23, 0xc3);
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WREG_CRT(24, vdisplay & 0xFF);
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WREG_ECRT(0x01, crtcext1);
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WREG_ECRT(0x02, crtcext2);
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WREG_ECRT(0x05, crtcext5);
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WREG8(MGA_MISC_OUT, misc);
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}
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static u8 mgag200_get_bpp_shift(const struct drm_format_info *format)
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{
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static const u8 bpp_shift[] = {0, 1, 0, 2};
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return bpp_shift[format->cpp[0] - 1];
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}
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/*
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* Calculates the HW offset value from the framebuffer's pitch. The
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* offset is a multiple of the pixel size and depends on the display
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* format.
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*/
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static u32 mgag200_calculate_offset(struct mga_device *mdev,
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const struct drm_framebuffer *fb)
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{
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u32 offset = fb->pitches[0] / fb->format->cpp[0];
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u8 bppshift = mgag200_get_bpp_shift(fb->format);
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if (fb->format->cpp[0] * 8 == 24)
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offset = (offset * 3) >> (4 - bppshift);
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else
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offset = offset >> (4 - bppshift);
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return offset;
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}
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static void mgag200_set_offset(struct mga_device *mdev,
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const struct drm_framebuffer *fb)
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{
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u8 crtc13, crtcext0;
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u32 offset = mgag200_calculate_offset(mdev, fb);
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RREG_ECRT(0, crtcext0);
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crtc13 = offset & 0xff;
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crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK;
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crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK;
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WREG_CRT(0x13, crtc13);
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WREG_ECRT(0x00, crtcext0);
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}
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void mgag200_set_format_regs(struct mga_device *mdev, const struct drm_format_info *format)
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{
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struct drm_device *dev = &mdev->base;
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unsigned int bpp, bppshift, scale;
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u8 crtcext3, xmulctrl;
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bpp = format->cpp[0] * 8;
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bppshift = mgag200_get_bpp_shift(format);
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switch (bpp) {
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case 24:
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scale = ((1 << bppshift) * 3) - 1;
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break;
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default:
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scale = (1 << bppshift) - 1;
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break;
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}
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RREG_ECRT(3, crtcext3);
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switch (bpp) {
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case 8:
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xmulctrl = MGA1064_MUL_CTL_8bits;
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break;
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case 16:
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if (format->depth == 15)
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xmulctrl = MGA1064_MUL_CTL_15bits;
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else
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xmulctrl = MGA1064_MUL_CTL_16bits;
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break;
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case 24:
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xmulctrl = MGA1064_MUL_CTL_24bits;
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break;
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case 32:
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xmulctrl = MGA1064_MUL_CTL_32_24bits;
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break;
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default:
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/* BUG: We should have caught this problem already. */
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drm_WARN_ON(dev, "invalid format depth\n");
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return;
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}
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crtcext3 &= ~GENMASK(2, 0);
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crtcext3 |= scale;
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WREG_DAC(MGA1064_MUL_CTL, xmulctrl);
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WREG_GFX(0, 0x00);
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WREG_GFX(1, 0x00);
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WREG_GFX(2, 0x00);
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WREG_GFX(3, 0x00);
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WREG_GFX(4, 0x00);
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WREG_GFX(5, 0x40);
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/* GCTL6 should be 0x05, but we configure memmapsl to 0xb8000 (text mode),
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* so that it doesn't hang when running kexec/kdump on G200_SE rev42.
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*/
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WREG_GFX(6, 0x0d);
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WREG_GFX(7, 0x0f);
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WREG_GFX(8, 0x0f);
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WREG_ECRT(3, crtcext3);
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}
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void mgag200_enable_display(struct mga_device *mdev)
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{
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u8 seq0, crtcext1;
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RREG_SEQ(0x00, seq0);
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seq0 |= MGAREG_SEQ0_SYNCRST |
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MGAREG_SEQ0_ASYNCRST;
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WREG_SEQ(0x00, seq0);
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/*
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* TODO: replace busy waiting with vblank IRQ; put
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* msleep(50) before changing SCROFF
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*/
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mga_wait_vsync(mdev);
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mga_wait_busy(mdev);
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RREG_ECRT(0x01, crtcext1);
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crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF;
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crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF;
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WREG_ECRT(0x01, crtcext1);
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}
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static void mgag200_disable_display(struct mga_device *mdev)
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{
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u8 seq0, crtcext1;
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RREG_SEQ(0x00, seq0);
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seq0 &= ~MGAREG_SEQ0_SYNCRST;
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WREG_SEQ(0x00, seq0);
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/*
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* TODO: replace busy waiting with vblank IRQ; put
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* msleep(50) before changing SCROFF
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*/
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mga_wait_vsync(mdev);
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mga_wait_busy(mdev);
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RREG_ECRT(0x01, crtcext1);
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crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF |
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MGAREG_CRTCEXT1_HSYNCOFF;
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WREG_ECRT(0x01, crtcext1);
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}
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static void mgag200_handle_damage(struct mga_device *mdev, const struct iosys_map *vmap,
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struct drm_framebuffer *fb, struct drm_rect *clip)
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{
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struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(mdev->vram);
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iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, clip));
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drm_fb_memcpy(&dst, fb->pitches, vmap, fb, clip);
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}
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/*
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* Primary plane
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*/
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const uint32_t mgag200_primary_plane_formats[] = {
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_RGB565,
|
|
DRM_FORMAT_RGB888,
|
|
};
|
|
|
|
const size_t mgag200_primary_plane_formats_size = ARRAY_SIZE(mgag200_primary_plane_formats);
|
|
|
|
const uint64_t mgag200_primary_plane_fmtmods[] = {
|
|
DRM_FORMAT_MOD_LINEAR,
|
|
DRM_FORMAT_MOD_INVALID
|
|
};
|
|
|
|
int mgag200_primary_plane_helper_atomic_check(struct drm_plane *plane,
|
|
struct drm_atomic_state *new_state)
|
|
{
|
|
struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(new_state, plane);
|
|
struct drm_framebuffer *new_fb = new_plane_state->fb;
|
|
struct drm_framebuffer *fb = NULL;
|
|
struct drm_crtc *new_crtc = new_plane_state->crtc;
|
|
struct drm_crtc_state *new_crtc_state = NULL;
|
|
struct mgag200_crtc_state *new_mgag200_crtc_state;
|
|
int ret;
|
|
|
|
if (new_crtc)
|
|
new_crtc_state = drm_atomic_get_new_crtc_state(new_state, new_crtc);
|
|
|
|
ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state,
|
|
DRM_PLANE_NO_SCALING,
|
|
DRM_PLANE_NO_SCALING,
|
|
false, true);
|
|
if (ret)
|
|
return ret;
|
|
else if (!new_plane_state->visible)
|
|
return 0;
|
|
|
|
if (plane->state)
|
|
fb = plane->state->fb;
|
|
|
|
if (!fb || (fb->format != new_fb->format))
|
|
new_crtc_state->mode_changed = true; /* update PLL settings */
|
|
|
|
new_mgag200_crtc_state = to_mgag200_crtc_state(new_crtc_state);
|
|
new_mgag200_crtc_state->format = new_fb->format;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane,
|
|
struct drm_atomic_state *old_state)
|
|
{
|
|
struct drm_device *dev = plane->dev;
|
|
struct mga_device *mdev = to_mga_device(dev);
|
|
struct drm_plane_state *plane_state = plane->state;
|
|
struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(old_state, plane);
|
|
struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
|
|
struct drm_framebuffer *fb = plane_state->fb;
|
|
struct drm_atomic_helper_damage_iter iter;
|
|
struct drm_rect damage;
|
|
u8 seq1;
|
|
|
|
if (!fb)
|
|
return;
|
|
|
|
drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
|
|
drm_atomic_for_each_plane_damage(&iter, &damage) {
|
|
mgag200_handle_damage(mdev, shadow_plane_state->data, fb, &damage);
|
|
}
|
|
|
|
/* Always scanout image at VRAM offset 0 */
|
|
mgag200_set_startadd(mdev, (u32)0);
|
|
mgag200_set_offset(mdev, fb);
|
|
|
|
if (!old_plane_state->crtc && plane_state->crtc) { // enabling
|
|
RREG_SEQ(0x01, seq1);
|
|
seq1 &= ~MGAREG_SEQ1_SCROFF;
|
|
WREG_SEQ(0x01, seq1);
|
|
msleep(20);
|
|
}
|
|
}
|
|
|
|
void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane,
|
|
struct drm_atomic_state *old_state)
|
|
{
|
|
struct drm_device *dev = plane->dev;
|
|
struct mga_device *mdev = to_mga_device(dev);
|
|
u8 seq1;
|
|
|
|
RREG_SEQ(0x01, seq1);
|
|
seq1 |= MGAREG_SEQ1_SCROFF;
|
|
WREG_SEQ(0x01, seq1);
|
|
msleep(20);
|
|
}
|
|
|
|
/*
|
|
* CRTC
|
|
*/
|
|
|
|
enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc,
|
|
const struct drm_display_mode *mode)
|
|
{
|
|
struct mga_device *mdev = to_mga_device(crtc->dev);
|
|
const struct mgag200_device_info *info = mdev->info;
|
|
|
|
/*
|
|
* Some devices have additional limits on the size of the
|
|
* display mode.
|
|
*/
|
|
if (mode->hdisplay > info->max_hdisplay)
|
|
return MODE_VIRTUAL_X;
|
|
if (mode->vdisplay > info->max_vdisplay)
|
|
return MODE_VIRTUAL_Y;
|
|
|
|
if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
|
|
(mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
|
|
return MODE_H_ILLEGAL;
|
|
}
|
|
|
|
if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
|
|
mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
|
|
mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
|
|
mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
|
|
return MODE_BAD;
|
|
}
|
|
|
|
return MODE_OK;
|
|
}
|
|
|
|
int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct mga_device *mdev = to_mga_device(dev);
|
|
const struct mgag200_device_funcs *funcs = mdev->funcs;
|
|
struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(new_state, crtc);
|
|
struct drm_property_blob *new_gamma_lut = new_crtc_state->gamma_lut;
|
|
int ret;
|
|
|
|
if (!new_crtc_state->enable)
|
|
return 0;
|
|
|
|
ret = drm_atomic_helper_check_crtc_primary_plane(new_crtc_state);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (new_crtc_state->mode_changed) {
|
|
if (funcs->pixpllc_atomic_check) {
|
|
ret = funcs->pixpllc_atomic_check(crtc, new_state);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (new_crtc_state->color_mgmt_changed && new_gamma_lut) {
|
|
if (new_gamma_lut->length != MGAG200_LUT_SIZE * sizeof(struct drm_color_lut)) {
|
|
drm_dbg(dev, "Wrong size for gamma_lut %zu\n", new_gamma_lut->length);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *old_state)
|
|
{
|
|
struct drm_crtc_state *crtc_state = crtc->state;
|
|
struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);
|
|
struct drm_device *dev = crtc->dev;
|
|
struct mga_device *mdev = to_mga_device(dev);
|
|
|
|
if (crtc_state->enable && crtc_state->color_mgmt_changed) {
|
|
const struct drm_format_info *format = mgag200_crtc_state->format;
|
|
|
|
if (crtc_state->gamma_lut)
|
|
mgag200_crtc_set_gamma(mdev, format, crtc_state->gamma_lut->data);
|
|
else
|
|
mgag200_crtc_set_gamma_linear(mdev, format);
|
|
}
|
|
}
|
|
|
|
void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *old_state)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct mga_device *mdev = to_mga_device(dev);
|
|
const struct mgag200_device_funcs *funcs = mdev->funcs;
|
|
struct drm_crtc_state *crtc_state = crtc->state;
|
|
struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
|
|
struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);
|
|
const struct drm_format_info *format = mgag200_crtc_state->format;
|
|
|
|
if (funcs->disable_vidrst)
|
|
funcs->disable_vidrst(mdev);
|
|
|
|
mgag200_set_format_regs(mdev, format);
|
|
mgag200_set_mode_regs(mdev, adjusted_mode);
|
|
|
|
if (funcs->pixpllc_atomic_update)
|
|
funcs->pixpllc_atomic_update(crtc, old_state);
|
|
|
|
mgag200_enable_display(mdev);
|
|
|
|
if (funcs->enable_vidrst)
|
|
funcs->enable_vidrst(mdev);
|
|
}
|
|
|
|
void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *old_state)
|
|
{
|
|
struct mga_device *mdev = to_mga_device(crtc->dev);
|
|
const struct mgag200_device_funcs *funcs = mdev->funcs;
|
|
|
|
if (funcs->disable_vidrst)
|
|
funcs->disable_vidrst(mdev);
|
|
|
|
mgag200_disable_display(mdev);
|
|
|
|
if (funcs->enable_vidrst)
|
|
funcs->enable_vidrst(mdev);
|
|
}
|
|
|
|
void mgag200_crtc_reset(struct drm_crtc *crtc)
|
|
{
|
|
struct mgag200_crtc_state *mgag200_crtc_state;
|
|
|
|
if (crtc->state)
|
|
crtc->funcs->atomic_destroy_state(crtc, crtc->state);
|
|
|
|
mgag200_crtc_state = kzalloc(sizeof(*mgag200_crtc_state), GFP_KERNEL);
|
|
if (mgag200_crtc_state)
|
|
__drm_atomic_helper_crtc_reset(crtc, &mgag200_crtc_state->base);
|
|
else
|
|
__drm_atomic_helper_crtc_reset(crtc, NULL);
|
|
}
|
|
|
|
struct drm_crtc_state *mgag200_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
|
|
{
|
|
struct drm_crtc_state *crtc_state = crtc->state;
|
|
struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);
|
|
struct mgag200_crtc_state *new_mgag200_crtc_state;
|
|
|
|
if (!crtc_state)
|
|
return NULL;
|
|
|
|
new_mgag200_crtc_state = kzalloc(sizeof(*new_mgag200_crtc_state), GFP_KERNEL);
|
|
if (!new_mgag200_crtc_state)
|
|
return NULL;
|
|
__drm_atomic_helper_crtc_duplicate_state(crtc, &new_mgag200_crtc_state->base);
|
|
|
|
new_mgag200_crtc_state->format = mgag200_crtc_state->format;
|
|
memcpy(&new_mgag200_crtc_state->pixpllc, &mgag200_crtc_state->pixpllc,
|
|
sizeof(new_mgag200_crtc_state->pixpllc));
|
|
|
|
return &new_mgag200_crtc_state->base;
|
|
}
|
|
|
|
void mgag200_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state)
|
|
{
|
|
struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);
|
|
|
|
__drm_atomic_helper_crtc_destroy_state(&mgag200_crtc_state->base);
|
|
kfree(mgag200_crtc_state);
|
|
}
|
|
|
|
/*
|
|
* Connector
|
|
*/
|
|
|
|
int mgag200_vga_connector_helper_get_modes(struct drm_connector *connector)
|
|
{
|
|
struct mga_device *mdev = to_mga_device(connector->dev);
|
|
int ret;
|
|
|
|
/*
|
|
* Protect access to I/O registers from concurrent modesetting
|
|
* by acquiring the I/O-register lock.
|
|
*/
|
|
mutex_lock(&mdev->rmmio_lock);
|
|
ret = drm_connector_helper_get_modes_from_ddc(connector);
|
|
mutex_unlock(&mdev->rmmio_lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Mode config
|
|
*/
|
|
|
|
static void mgag200_mode_config_helper_atomic_commit_tail(struct drm_atomic_state *state)
|
|
{
|
|
struct mga_device *mdev = to_mga_device(state->dev);
|
|
|
|
/*
|
|
* Concurrent operations could possibly trigger a call to
|
|
* drm_connector_helper_funcs.get_modes by trying to read the
|
|
* display modes. Protect access to I/O registers by acquiring
|
|
* the I/O-register lock.
|
|
*/
|
|
mutex_lock(&mdev->rmmio_lock);
|
|
drm_atomic_helper_commit_tail(state);
|
|
mutex_unlock(&mdev->rmmio_lock);
|
|
}
|
|
|
|
static const struct drm_mode_config_helper_funcs mgag200_mode_config_helper_funcs = {
|
|
.atomic_commit_tail = mgag200_mode_config_helper_atomic_commit_tail,
|
|
};
|
|
|
|
/* Calculates a mode's required memory bandwidth (in KiB/sec). */
|
|
static uint32_t mgag200_calculate_mode_bandwidth(const struct drm_display_mode *mode,
|
|
unsigned int bits_per_pixel)
|
|
{
|
|
uint32_t total_area, divisor;
|
|
uint64_t active_area, pixels_per_second, bandwidth;
|
|
uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
|
|
|
|
divisor = 1024;
|
|
|
|
if (!mode->htotal || !mode->vtotal || !mode->clock)
|
|
return 0;
|
|
|
|
active_area = mode->hdisplay * mode->vdisplay;
|
|
total_area = mode->htotal * mode->vtotal;
|
|
|
|
pixels_per_second = active_area * mode->clock * 1000;
|
|
do_div(pixels_per_second, total_area);
|
|
|
|
bandwidth = pixels_per_second * bytes_per_pixel * 100;
|
|
do_div(bandwidth, divisor);
|
|
|
|
return (uint32_t)bandwidth;
|
|
}
|
|
|
|
static enum drm_mode_status mgag200_mode_config_mode_valid(struct drm_device *dev,
|
|
const struct drm_display_mode *mode)
|
|
{
|
|
static const unsigned int max_bpp = 4; // DRM_FORMAT_XRGB8888
|
|
struct mga_device *mdev = to_mga_device(dev);
|
|
unsigned long fbsize, fbpages, max_fbpages;
|
|
const struct mgag200_device_info *info = mdev->info;
|
|
|
|
max_fbpages = mdev->vram_available >> PAGE_SHIFT;
|
|
|
|
fbsize = mode->hdisplay * mode->vdisplay * max_bpp;
|
|
fbpages = DIV_ROUND_UP(fbsize, PAGE_SIZE);
|
|
|
|
if (fbpages > max_fbpages)
|
|
return MODE_MEM;
|
|
|
|
/*
|
|
* Test the mode's required memory bandwidth if the device
|
|
* specifies a maximum. Not all devices do though.
|
|
*/
|
|
if (info->max_mem_bandwidth) {
|
|
uint32_t mode_bandwidth = mgag200_calculate_mode_bandwidth(mode, max_bpp * 8);
|
|
|
|
if (mode_bandwidth > (info->max_mem_bandwidth * 1024))
|
|
return MODE_BAD;
|
|
}
|
|
|
|
return MODE_OK;
|
|
}
|
|
|
|
static const struct drm_mode_config_funcs mgag200_mode_config_funcs = {
|
|
.fb_create = drm_gem_fb_create_with_dirty,
|
|
.mode_valid = mgag200_mode_config_mode_valid,
|
|
.atomic_check = drm_atomic_helper_check,
|
|
.atomic_commit = drm_atomic_helper_commit,
|
|
};
|
|
|
|
int mgag200_mode_config_init(struct mga_device *mdev, resource_size_t vram_available)
|
|
{
|
|
struct drm_device *dev = &mdev->base;
|
|
int ret;
|
|
|
|
mdev->vram_available = vram_available;
|
|
|
|
ret = drmm_mode_config_init(dev);
|
|
if (ret) {
|
|
drm_err(dev, "drmm_mode_config_init() failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
|
|
dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
|
|
dev->mode_config.preferred_depth = 24;
|
|
dev->mode_config.funcs = &mgag200_mode_config_funcs;
|
|
dev->mode_config.helper_private = &mgag200_mode_config_helper_funcs;
|
|
|
|
return 0;
|
|
}
|