mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-30 12:49:36 +00:00
![Danilo Krummrich](/assets/img/avatar_default.png)
Rename "GEM CMA" helpers to "GEM DMA" helpers - considering the
hierarchy of APIs (mm/cma -> dma -> gem dma) calling them "GEM
DMA" seems to be more applicable.
Besides that, commit e57924d4ae
("drm/doc: Task to rename CMA helpers")
requests to rename the CMA helpers and implies that people seem to be
confused about the naming.
In order to do this renaming the following script was used:
```
#!/bin/bash
DIRS="drivers/gpu include/drm Documentation/gpu"
REGEX_SYM_UPPER="[0-9A-Z_\-]"
REGEX_SYM_LOWER="[0-9a-z_\-]"
REGEX_GREP_UPPER="(${REGEX_SYM_UPPER}*)(GEM)_CMA_(${REGEX_SYM_UPPER}*)"
REGEX_GREP_LOWER="(${REGEX_SYM_LOWER}*)(gem)_cma_(${REGEX_SYM_LOWER}*)"
REGEX_SED_UPPER="s/${REGEX_GREP_UPPER}/\1\2_DMA_\3/g"
REGEX_SED_LOWER="s/${REGEX_GREP_LOWER}/\1\2_dma_\3/g"
# Find all upper case 'CMA' symbols and replace them with 'DMA'.
for ff in $(grep -REHl "${REGEX_GREP_UPPER}" $DIRS)
do
sed -i -E "$REGEX_SED_UPPER" $ff
done
# Find all lower case 'cma' symbols and replace them with 'dma'.
for ff in $(grep -REHl "${REGEX_GREP_LOWER}" $DIRS)
do
sed -i -E "$REGEX_SED_LOWER" $ff
done
# Replace all occurrences of 'CMA' / 'cma' in comments and
# documentation files with 'DMA' / 'dma'.
for ff in $(grep -RiHl " cma " $DIRS)
do
sed -i -E "s/ cma / dma /g" $ff
sed -i -E "s/ CMA / DMA /g" $ff
done
# Rename all 'cma_obj's to 'dma_obj'.
for ff in $(grep -RiHl "cma_obj" $DIRS)
do
sed -i -E "s/cma_obj/dma_obj/g" $ff
done
```
Only a few more manual modifications were needed, e.g. reverting the
following modifications in some DRM Kconfig files
- select CMA if HAVE_DMA_CONTIGUOUS
+ select DMA if HAVE_DMA_CONTIGUOUS
as well as manually picking the occurrences of 'CMA'/'cma' in comments and
documentation which relate to "GEM CMA", but not "FB CMA".
Also drivers/gpu/drm/Makefile was fixed up manually after renaming
drm_gem_cma_helper.c to drm_gem_dma_helper.c.
This patch is compile-time tested building a x86_64 kernel with
`make allyesconfig && make drivers/gpu/drm`.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Danilo Krummrich <dakr@redhat.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com> #drivers/gpu/drm/arm
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220802000405.949236-4-dakr@redhat.com
596 lines
15 KiB
C
596 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
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*
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* Parts of this file were based on sources as follows:
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*
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* Copyright (c) 2006-2008 Intel Corporation
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* Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
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* Copyright (C) 2011 Texas Instruments
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-buf.h>
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#include <linux/media-bus-format.h>
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#include <linux/of_graph.h>
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#include <drm/drm_fb_dma_helper.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_framebuffer.h>
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#include <drm/drm_gem_atomic_helper.h>
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#include <drm/drm_gem_dma_helper.h>
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#include <drm/drm_vblank.h>
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#include "pl111_drm.h"
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irqreturn_t pl111_irq(int irq, void *data)
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{
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struct pl111_drm_dev_private *priv = data;
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u32 irq_stat;
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irqreturn_t status = IRQ_NONE;
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irq_stat = readl(priv->regs + CLCD_PL111_MIS);
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if (!irq_stat)
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return IRQ_NONE;
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if (irq_stat & CLCD_IRQ_NEXTBASE_UPDATE) {
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drm_crtc_handle_vblank(&priv->pipe.crtc);
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status = IRQ_HANDLED;
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}
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/* Clear the interrupt once done */
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writel(irq_stat, priv->regs + CLCD_PL111_ICR);
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return status;
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}
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static enum drm_mode_status
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pl111_mode_valid(struct drm_simple_display_pipe *pipe,
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const struct drm_display_mode *mode)
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{
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struct drm_device *drm = pipe->crtc.dev;
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struct pl111_drm_dev_private *priv = drm->dev_private;
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u32 cpp = priv->variant->fb_bpp / 8;
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u64 bw;
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/*
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* We use the pixelclock to also account for interlaced modes, the
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* resulting bandwidth is in bytes per second.
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*/
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bw = mode->clock * 1000ULL; /* In Hz */
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bw = bw * mode->hdisplay * mode->vdisplay * cpp;
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bw = div_u64(bw, mode->htotal * mode->vtotal);
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/*
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* If no bandwidth constraints, anything goes, else
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* check if we are too fast.
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*/
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if (priv->memory_bw && (bw > priv->memory_bw)) {
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DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu too fast\n",
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mode->hdisplay, mode->vdisplay,
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mode->clock * 1000, cpp, bw);
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return MODE_BAD;
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}
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DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu bytes/s OK\n",
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mode->hdisplay, mode->vdisplay,
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mode->clock * 1000, cpp, bw);
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return MODE_OK;
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}
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static int pl111_display_check(struct drm_simple_display_pipe *pipe,
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struct drm_plane_state *pstate,
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struct drm_crtc_state *cstate)
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{
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const struct drm_display_mode *mode = &cstate->mode;
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struct drm_framebuffer *old_fb = pipe->plane.state->fb;
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struct drm_framebuffer *fb = pstate->fb;
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if (mode->hdisplay % 16)
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return -EINVAL;
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if (fb) {
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u32 offset = drm_fb_dma_get_gem_addr(fb, pstate, 0);
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/* FB base address must be dword aligned. */
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if (offset & 3)
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return -EINVAL;
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/* There's no pitch register -- the mode's hdisplay
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* controls it.
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*/
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if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0])
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return -EINVAL;
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/* We can't change the FB format in a flicker-free
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* manner (and only update it during CRTC enable).
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*/
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if (old_fb && old_fb->format != fb->format)
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cstate->mode_changed = true;
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}
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return 0;
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}
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static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
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struct drm_crtc_state *cstate,
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struct drm_plane_state *plane_state)
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{
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struct drm_crtc *crtc = &pipe->crtc;
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struct drm_plane *plane = &pipe->plane;
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struct drm_device *drm = crtc->dev;
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struct pl111_drm_dev_private *priv = drm->dev_private;
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const struct drm_display_mode *mode = &cstate->mode;
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struct drm_framebuffer *fb = plane->state->fb;
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struct drm_connector *connector = priv->connector;
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struct drm_bridge *bridge = priv->bridge;
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bool grayscale = false;
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u32 cntl;
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u32 ppl, hsw, hfp, hbp;
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u32 lpp, vsw, vfp, vbp;
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u32 cpl, tim2;
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int ret;
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ret = clk_set_rate(priv->clk, mode->clock * 1000);
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if (ret) {
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dev_err(drm->dev,
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"Failed to set pixel clock rate to %d: %d\n",
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mode->clock * 1000, ret);
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}
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clk_prepare_enable(priv->clk);
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ppl = (mode->hdisplay / 16) - 1;
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hsw = mode->hsync_end - mode->hsync_start - 1;
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hfp = mode->hsync_start - mode->hdisplay - 1;
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hbp = mode->htotal - mode->hsync_end - 1;
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lpp = mode->vdisplay - 1;
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vsw = mode->vsync_end - mode->vsync_start - 1;
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vfp = mode->vsync_start - mode->vdisplay;
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vbp = mode->vtotal - mode->vsync_end;
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cpl = mode->hdisplay - 1;
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writel((ppl << 2) |
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(hsw << 8) |
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(hfp << 16) |
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(hbp << 24),
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priv->regs + CLCD_TIM0);
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writel(lpp |
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(vsw << 10) |
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(vfp << 16) |
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(vbp << 24),
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priv->regs + CLCD_TIM1);
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spin_lock(&priv->tim2_lock);
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tim2 = readl(priv->regs + CLCD_TIM2);
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tim2 &= (TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK);
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if (priv->variant->broken_clockdivider)
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tim2 |= TIM2_BCD;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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tim2 |= TIM2_IHS;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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tim2 |= TIM2_IVS;
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if (connector) {
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if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
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tim2 |= TIM2_IOE;
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if (connector->display_info.bus_flags &
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DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
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tim2 |= TIM2_IPC;
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if (connector->display_info.num_bus_formats == 1 &&
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connector->display_info.bus_formats[0] ==
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MEDIA_BUS_FMT_Y8_1X8)
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grayscale = true;
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/*
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* The AC pin bias frequency is set to max count when using
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* grayscale so at least once in a while we will reverse
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* polarity and get rid of any DC built up that could
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* damage the display.
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*/
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if (grayscale)
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tim2 |= TIM2_ACB_MASK;
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}
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if (bridge) {
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const struct drm_bridge_timings *btimings = bridge->timings;
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/*
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* Here is when things get really fun. Sometimes the bridge
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* timings are such that the signal out from PL11x is not
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* stable before the receiving bridge (such as a dumb VGA DAC
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* or similar) samples it. If that happens, we compensate by
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* the only method we have: output the data on the opposite
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* edge of the clock so it is for sure stable when it gets
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* sampled.
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*
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* The PL111 manual does not contain proper timining diagrams
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* or data for these details, but we know from experiments
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* that the setup time is more than 3000 picoseconds (3 ns).
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* If we have a bridge that requires the signal to be stable
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* earlier than 3000 ps before the clock pulse, we have to
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* output the data on the opposite edge to avoid flicker.
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*/
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if (btimings && btimings->setup_time_ps >= 3000)
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tim2 ^= TIM2_IPC;
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}
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tim2 |= cpl << 16;
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writel(tim2, priv->regs + CLCD_TIM2);
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spin_unlock(&priv->tim2_lock);
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writel(0, priv->regs + CLCD_TIM3);
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/*
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* Detect grayscale bus format. We do not support a grayscale mode
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* toward userspace, instead we expose an RGB24 buffer and then the
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* hardware will activate its grayscaler to convert to the grayscale
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* format.
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*/
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if (grayscale)
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cntl = CNTL_LCDEN | CNTL_LCDMONO8;
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else
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/* Else we assume TFT display */
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cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1);
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/* On the ST Micro variant, assume all 24 bits are connected */
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if (priv->variant->st_bitmux_control)
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cntl |= CNTL_ST_CDWID_24;
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/*
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* Note that the ARM hardware's format reader takes 'r' from
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* the low bit, while DRM formats list channels from high bit
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* to low bit as you read left to right. The ST Micro version of
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* the PL110 (LCDC) however uses the standard DRM format.
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*/
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switch (fb->format->format) {
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case DRM_FORMAT_BGR888:
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/* Only supported on the ST Micro variant */
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if (priv->variant->st_bitmux_control)
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cntl |= CNTL_ST_LCDBPP24_PACKED | CNTL_BGR;
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break;
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case DRM_FORMAT_RGB888:
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/* Only supported on the ST Micro variant */
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if (priv->variant->st_bitmux_control)
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cntl |= CNTL_ST_LCDBPP24_PACKED;
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break;
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case DRM_FORMAT_ABGR8888:
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case DRM_FORMAT_XBGR8888:
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if (priv->variant->st_bitmux_control)
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cntl |= CNTL_LCDBPP24 | CNTL_BGR;
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else
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cntl |= CNTL_LCDBPP24;
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break;
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_XRGB8888:
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if (priv->variant->st_bitmux_control)
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cntl |= CNTL_LCDBPP24;
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else
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cntl |= CNTL_LCDBPP24 | CNTL_BGR;
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break;
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case DRM_FORMAT_BGR565:
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if (priv->variant->is_pl110)
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cntl |= CNTL_LCDBPP16;
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else if (priv->variant->st_bitmux_control)
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cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565 | CNTL_BGR;
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else
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cntl |= CNTL_LCDBPP16_565;
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break;
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case DRM_FORMAT_RGB565:
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if (priv->variant->is_pl110)
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cntl |= CNTL_LCDBPP16 | CNTL_BGR;
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else if (priv->variant->st_bitmux_control)
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cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565;
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else
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cntl |= CNTL_LCDBPP16_565 | CNTL_BGR;
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break;
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case DRM_FORMAT_ABGR1555:
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case DRM_FORMAT_XBGR1555:
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cntl |= CNTL_LCDBPP16;
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if (priv->variant->st_bitmux_control)
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cntl |= CNTL_ST_1XBPP_5551 | CNTL_BGR;
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break;
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case DRM_FORMAT_ARGB1555:
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case DRM_FORMAT_XRGB1555:
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cntl |= CNTL_LCDBPP16;
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if (priv->variant->st_bitmux_control)
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cntl |= CNTL_ST_1XBPP_5551;
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else
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cntl |= CNTL_BGR;
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break;
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case DRM_FORMAT_ABGR4444:
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case DRM_FORMAT_XBGR4444:
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cntl |= CNTL_LCDBPP16_444;
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if (priv->variant->st_bitmux_control)
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cntl |= CNTL_ST_1XBPP_444 | CNTL_BGR;
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break;
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case DRM_FORMAT_ARGB4444:
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case DRM_FORMAT_XRGB4444:
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cntl |= CNTL_LCDBPP16_444;
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if (priv->variant->st_bitmux_control)
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cntl |= CNTL_ST_1XBPP_444;
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else
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cntl |= CNTL_BGR;
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break;
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default:
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WARN_ONCE(true, "Unknown FB format 0x%08x\n",
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fb->format->format);
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break;
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}
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/* The PL110 in Integrator/Versatile does the BGR routing externally */
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if (priv->variant->external_bgr)
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cntl &= ~CNTL_BGR;
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/* Power sequence: first enable and chill */
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writel(cntl, priv->regs + priv->ctrl);
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/*
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* We expect this delay to stabilize the contrast
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* voltage Vee as stipulated by the manual
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*/
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msleep(20);
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if (priv->variant_display_enable)
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priv->variant_display_enable(drm, fb->format->format);
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/* Power Up */
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cntl |= CNTL_LCDPWR;
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writel(cntl, priv->regs + priv->ctrl);
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if (!priv->variant->broken_vblank)
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drm_crtc_vblank_on(crtc);
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}
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static void pl111_display_disable(struct drm_simple_display_pipe *pipe)
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{
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struct drm_crtc *crtc = &pipe->crtc;
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struct drm_device *drm = crtc->dev;
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struct pl111_drm_dev_private *priv = drm->dev_private;
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u32 cntl;
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if (!priv->variant->broken_vblank)
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drm_crtc_vblank_off(crtc);
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/* Power Down */
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cntl = readl(priv->regs + priv->ctrl);
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if (cntl & CNTL_LCDPWR) {
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cntl &= ~CNTL_LCDPWR;
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writel(cntl, priv->regs + priv->ctrl);
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}
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/*
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* We expect this delay to stabilize the contrast voltage Vee as
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* stipulated by the manual
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*/
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msleep(20);
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if (priv->variant_display_disable)
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priv->variant_display_disable(drm);
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/* Disable */
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writel(0, priv->regs + priv->ctrl);
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clk_disable_unprepare(priv->clk);
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}
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static void pl111_display_update(struct drm_simple_display_pipe *pipe,
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struct drm_plane_state *old_pstate)
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{
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struct drm_crtc *crtc = &pipe->crtc;
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struct drm_device *drm = crtc->dev;
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struct pl111_drm_dev_private *priv = drm->dev_private;
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struct drm_pending_vblank_event *event = crtc->state->event;
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struct drm_plane *plane = &pipe->plane;
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struct drm_plane_state *pstate = plane->state;
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struct drm_framebuffer *fb = pstate->fb;
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if (fb) {
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u32 addr = drm_fb_dma_get_gem_addr(fb, pstate, 0);
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writel(addr, priv->regs + CLCD_UBAS);
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}
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if (event) {
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crtc->state->event = NULL;
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spin_lock_irq(&crtc->dev->event_lock);
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if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0)
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drm_crtc_arm_vblank_event(crtc, event);
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else
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drm_crtc_send_vblank_event(crtc, event);
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spin_unlock_irq(&crtc->dev->event_lock);
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}
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}
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static int pl111_display_enable_vblank(struct drm_simple_display_pipe *pipe)
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{
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struct drm_crtc *crtc = &pipe->crtc;
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struct drm_device *drm = crtc->dev;
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struct pl111_drm_dev_private *priv = drm->dev_private;
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writel(CLCD_IRQ_NEXTBASE_UPDATE, priv->regs + priv->ienb);
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return 0;
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}
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static void pl111_display_disable_vblank(struct drm_simple_display_pipe *pipe)
|
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{
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struct drm_crtc *crtc = &pipe->crtc;
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struct drm_device *drm = crtc->dev;
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struct pl111_drm_dev_private *priv = drm->dev_private;
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|
|
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writel(0, priv->regs + priv->ienb);
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}
|
|
|
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static struct drm_simple_display_pipe_funcs pl111_display_funcs = {
|
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.mode_valid = pl111_mode_valid,
|
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.check = pl111_display_check,
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.enable = pl111_display_enable,
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.disable = pl111_display_disable,
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.update = pl111_display_update,
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|
};
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|
|
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static int pl111_clk_div_choose_div(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long *prate, bool set_parent)
|
|
{
|
|
int best_div = 1, div;
|
|
struct clk_hw *parent = clk_hw_get_parent(hw);
|
|
unsigned long best_prate = 0;
|
|
unsigned long best_diff = ~0ul;
|
|
int max_div = (1 << (TIM2_PCD_LO_BITS + TIM2_PCD_HI_BITS)) - 1;
|
|
|
|
for (div = 1; div < max_div; div++) {
|
|
unsigned long this_prate, div_rate, diff;
|
|
|
|
if (set_parent)
|
|
this_prate = clk_hw_round_rate(parent, rate * div);
|
|
else
|
|
this_prate = *prate;
|
|
div_rate = DIV_ROUND_UP_ULL(this_prate, div);
|
|
diff = abs(rate - div_rate);
|
|
|
|
if (diff < best_diff) {
|
|
best_div = div;
|
|
best_diff = diff;
|
|
best_prate = this_prate;
|
|
}
|
|
}
|
|
|
|
*prate = best_prate;
|
|
return best_div;
|
|
}
|
|
|
|
static long pl111_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long *prate)
|
|
{
|
|
int div = pl111_clk_div_choose_div(hw, rate, prate, true);
|
|
|
|
return DIV_ROUND_UP_ULL(*prate, div);
|
|
}
|
|
|
|
static unsigned long pl111_clk_div_recalc_rate(struct clk_hw *hw,
|
|
unsigned long prate)
|
|
{
|
|
struct pl111_drm_dev_private *priv =
|
|
container_of(hw, struct pl111_drm_dev_private, clk_div);
|
|
u32 tim2 = readl(priv->regs + CLCD_TIM2);
|
|
int div;
|
|
|
|
if (tim2 & TIM2_BCD)
|
|
return prate;
|
|
|
|
div = tim2 & TIM2_PCD_LO_MASK;
|
|
div |= (tim2 & TIM2_PCD_HI_MASK) >>
|
|
(TIM2_PCD_HI_SHIFT - TIM2_PCD_LO_BITS);
|
|
div += 2;
|
|
|
|
return DIV_ROUND_UP_ULL(prate, div);
|
|
}
|
|
|
|
static int pl111_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long prate)
|
|
{
|
|
struct pl111_drm_dev_private *priv =
|
|
container_of(hw, struct pl111_drm_dev_private, clk_div);
|
|
int div = pl111_clk_div_choose_div(hw, rate, &prate, false);
|
|
u32 tim2;
|
|
|
|
spin_lock(&priv->tim2_lock);
|
|
tim2 = readl(priv->regs + CLCD_TIM2);
|
|
tim2 &= ~(TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK);
|
|
|
|
if (div == 1) {
|
|
tim2 |= TIM2_BCD;
|
|
} else {
|
|
div -= 2;
|
|
tim2 |= div & TIM2_PCD_LO_MASK;
|
|
tim2 |= (div >> TIM2_PCD_LO_BITS) << TIM2_PCD_HI_SHIFT;
|
|
}
|
|
|
|
writel(tim2, priv->regs + CLCD_TIM2);
|
|
spin_unlock(&priv->tim2_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct clk_ops pl111_clk_div_ops = {
|
|
.recalc_rate = pl111_clk_div_recalc_rate,
|
|
.round_rate = pl111_clk_div_round_rate,
|
|
.set_rate = pl111_clk_div_set_rate,
|
|
};
|
|
|
|
static int
|
|
pl111_init_clock_divider(struct drm_device *drm)
|
|
{
|
|
struct pl111_drm_dev_private *priv = drm->dev_private;
|
|
struct clk *parent = devm_clk_get(drm->dev, "clcdclk");
|
|
struct clk_hw *div = &priv->clk_div;
|
|
const char *parent_name;
|
|
struct clk_init_data init = {
|
|
.name = "pl111_div",
|
|
.ops = &pl111_clk_div_ops,
|
|
.parent_names = &parent_name,
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
};
|
|
int ret;
|
|
|
|
if (IS_ERR(parent)) {
|
|
dev_err(drm->dev, "CLCD: unable to get clcdclk.\n");
|
|
return PTR_ERR(parent);
|
|
}
|
|
|
|
spin_lock_init(&priv->tim2_lock);
|
|
|
|
/* If the clock divider is broken, use the parent directly */
|
|
if (priv->variant->broken_clockdivider) {
|
|
priv->clk = parent;
|
|
return 0;
|
|
}
|
|
parent_name = __clk_get_name(parent);
|
|
div->init = &init;
|
|
|
|
ret = devm_clk_hw_register(drm->dev, div);
|
|
|
|
priv->clk = div->clk;
|
|
return ret;
|
|
}
|
|
|
|
int pl111_display_init(struct drm_device *drm)
|
|
{
|
|
struct pl111_drm_dev_private *priv = drm->dev_private;
|
|
int ret;
|
|
|
|
ret = pl111_init_clock_divider(drm);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!priv->variant->broken_vblank) {
|
|
pl111_display_funcs.enable_vblank = pl111_display_enable_vblank;
|
|
pl111_display_funcs.disable_vblank = pl111_display_disable_vblank;
|
|
}
|
|
|
|
ret = drm_simple_display_pipe_init(drm, &priv->pipe,
|
|
&pl111_display_funcs,
|
|
priv->variant->formats,
|
|
priv->variant->nformats,
|
|
NULL,
|
|
priv->connector);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|