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![Laurent Pinchart](/assets/img/avatar_default.png)
Add partial live video support, with a single video input that bypasses blending. Skip registration of the DRM device in that case, but register the DRM bridge instead. The DRM device will be created by the driver for the display controller in the PL. Full live video mode with concurrent usage of the video and gfx inputs, and blending in the DPSUB video pipeline, is currently unsupported. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
336 lines
8 KiB
C
336 lines
8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* ZynqMP DisplayPort Subsystem Driver
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*
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* Copyright (C) 2017 - 2020 Xilinx, Inc.
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*
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* Authors:
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* - Hyun Woo Kwon <hyun.kwon@xilinx.com>
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* - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*/
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/of_graph.h>
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#include <linux/of_reserved_mem.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_modeset_helper.h>
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#include <drm/drm_module.h>
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#include "zynqmp_disp.h"
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#include "zynqmp_dp.h"
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#include "zynqmp_dpsub.h"
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#include "zynqmp_kms.h"
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/* -----------------------------------------------------------------------------
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* Power Management
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*/
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static int __maybe_unused zynqmp_dpsub_suspend(struct device *dev)
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{
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struct zynqmp_dpsub *dpsub = dev_get_drvdata(dev);
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if (!dpsub->drm)
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return 0;
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return drm_mode_config_helper_suspend(&dpsub->drm->dev);
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}
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static int __maybe_unused zynqmp_dpsub_resume(struct device *dev)
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{
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struct zynqmp_dpsub *dpsub = dev_get_drvdata(dev);
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if (!dpsub->drm)
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return 0;
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return drm_mode_config_helper_resume(&dpsub->drm->dev);
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}
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static const struct dev_pm_ops zynqmp_dpsub_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(zynqmp_dpsub_suspend, zynqmp_dpsub_resume)
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};
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/* -----------------------------------------------------------------------------
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* DPSUB Configuration
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*/
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/**
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* zynqmp_dpsub_audio_enabled - If the audio is enabled
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* @dpsub: DisplayPort subsystem
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*
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* Return if the audio is enabled depending on the audio clock.
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*
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* Return: true if audio is enabled, or false.
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*/
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bool zynqmp_dpsub_audio_enabled(struct zynqmp_dpsub *dpsub)
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{
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return !!dpsub->aud_clk;
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}
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/**
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* zynqmp_dpsub_get_audio_clk_rate - Get the current audio clock rate
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* @dpsub: DisplayPort subsystem
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*
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* Return: the current audio clock rate.
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*/
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unsigned int zynqmp_dpsub_get_audio_clk_rate(struct zynqmp_dpsub *dpsub)
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{
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if (zynqmp_dpsub_audio_enabled(dpsub))
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return 0;
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return clk_get_rate(dpsub->aud_clk);
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}
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/* -----------------------------------------------------------------------------
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* Probe & Remove
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*/
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static int zynqmp_dpsub_init_clocks(struct zynqmp_dpsub *dpsub)
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{
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int ret;
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dpsub->apb_clk = devm_clk_get(dpsub->dev, "dp_apb_clk");
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if (IS_ERR(dpsub->apb_clk))
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return PTR_ERR(dpsub->apb_clk);
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ret = clk_prepare_enable(dpsub->apb_clk);
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if (ret) {
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dev_err(dpsub->dev, "failed to enable the APB clock\n");
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return ret;
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}
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/*
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* Try the live PL video clock, and fall back to the PS clock if the
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* live PL video clock isn't valid.
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*/
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dpsub->vid_clk = devm_clk_get(dpsub->dev, "dp_live_video_in_clk");
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if (!IS_ERR(dpsub->vid_clk))
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dpsub->vid_clk_from_ps = false;
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else if (PTR_ERR(dpsub->vid_clk) == -EPROBE_DEFER)
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return PTR_ERR(dpsub->vid_clk);
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if (IS_ERR_OR_NULL(dpsub->vid_clk)) {
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dpsub->vid_clk = devm_clk_get(dpsub->dev, "dp_vtc_pixel_clk_in");
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if (IS_ERR(dpsub->vid_clk)) {
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dev_err(dpsub->dev, "failed to init any video clock\n");
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return PTR_ERR(dpsub->vid_clk);
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}
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dpsub->vid_clk_from_ps = true;
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}
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/*
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* Try the live PL audio clock, and fall back to the PS clock if the
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* live PL audio clock isn't valid. Missing audio clock disables audio
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* but isn't an error.
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*/
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dpsub->aud_clk = devm_clk_get(dpsub->dev, "dp_live_audio_aclk");
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if (!IS_ERR(dpsub->aud_clk)) {
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dpsub->aud_clk_from_ps = false;
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return 0;
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}
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dpsub->aud_clk = devm_clk_get(dpsub->dev, "dp_aud_clk");
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if (!IS_ERR(dpsub->aud_clk)) {
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dpsub->aud_clk_from_ps = true;
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return 0;
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}
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dev_info(dpsub->dev, "audio disabled due to missing clock\n");
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return 0;
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}
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static int zynqmp_dpsub_parse_dt(struct zynqmp_dpsub *dpsub)
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{
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struct device_node *np;
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unsigned int i;
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/*
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* For backward compatibility with old device trees that don't contain
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* ports, consider that only the DP output port is connected if no
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* ports child no exists.
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*/
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np = of_get_child_by_name(dpsub->dev->of_node, "ports");
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of_node_put(np);
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if (!np) {
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dev_warn(dpsub->dev, "missing ports, update DT bindings\n");
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dpsub->connected_ports = BIT(ZYNQMP_DPSUB_PORT_OUT_DP);
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dpsub->dma_enabled = true;
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return 0;
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}
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/* Check which ports are connected. */
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for (i = 0; i < ZYNQMP_DPSUB_NUM_PORTS; ++i) {
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struct device_node *np;
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np = of_graph_get_remote_node(dpsub->dev->of_node, i, -1);
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if (np) {
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dpsub->connected_ports |= BIT(i);
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of_node_put(np);
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}
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}
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/* Sanity checks. */
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if ((dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_VIDEO)) &&
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(dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_GFX))) {
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dev_err(dpsub->dev, "only one live video input is supported\n");
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return -EINVAL;
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}
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if ((dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_VIDEO)) ||
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(dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_GFX))) {
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if (dpsub->vid_clk_from_ps) {
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dev_err(dpsub->dev,
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"live video input requires PL clock\n");
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return -EINVAL;
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}
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} else {
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dpsub->dma_enabled = true;
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}
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if (dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_AUDIO))
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dev_warn(dpsub->dev, "live audio unsupported, ignoring\n");
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if ((dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_OUT_VIDEO)) ||
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(dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_OUT_AUDIO)))
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dev_warn(dpsub->dev, "output to PL unsupported, ignoring\n");
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if (!(dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_OUT_DP))) {
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dev_err(dpsub->dev, "DP output port not connected\n");
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return -EINVAL;
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}
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return 0;
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}
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void zynqmp_dpsub_release(struct zynqmp_dpsub *dpsub)
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{
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kfree(dpsub->disp);
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kfree(dpsub->dp);
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kfree(dpsub);
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}
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static int zynqmp_dpsub_probe(struct platform_device *pdev)
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{
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struct zynqmp_dpsub *dpsub;
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int ret;
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/* Allocate private data. */
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dpsub = kzalloc(sizeof(*dpsub), GFP_KERNEL);
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if (!dpsub)
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return -ENOMEM;
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dpsub->dev = &pdev->dev;
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platform_set_drvdata(pdev, dpsub);
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dma_set_mask(dpsub->dev, DMA_BIT_MASK(ZYNQMP_DISP_MAX_DMA_BIT));
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/* Try the reserved memory. Proceed if there's none. */
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of_reserved_mem_device_init(&pdev->dev);
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ret = zynqmp_dpsub_init_clocks(dpsub);
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if (ret < 0)
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goto err_mem;
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ret = zynqmp_dpsub_parse_dt(dpsub);
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if (ret < 0)
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goto err_mem;
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pm_runtime_enable(&pdev->dev);
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/*
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* DP should be probed first so that the zynqmp_disp can set the output
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* format accordingly.
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*/
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ret = zynqmp_dp_probe(dpsub);
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if (ret)
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goto err_pm;
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ret = zynqmp_disp_probe(dpsub);
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if (ret)
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goto err_dp;
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if (dpsub->dma_enabled) {
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ret = zynqmp_dpsub_drm_init(dpsub);
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if (ret)
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goto err_disp;
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} else {
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drm_bridge_add(dpsub->bridge);
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}
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dev_info(&pdev->dev, "ZynqMP DisplayPort Subsystem driver probed");
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return 0;
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err_disp:
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zynqmp_disp_remove(dpsub);
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err_dp:
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zynqmp_dp_remove(dpsub);
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err_pm:
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pm_runtime_disable(&pdev->dev);
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clk_disable_unprepare(dpsub->apb_clk);
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err_mem:
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of_reserved_mem_device_release(&pdev->dev);
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if (!dpsub->drm)
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zynqmp_dpsub_release(dpsub);
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return ret;
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}
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static int zynqmp_dpsub_remove(struct platform_device *pdev)
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{
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struct zynqmp_dpsub *dpsub = platform_get_drvdata(pdev);
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if (dpsub->drm)
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zynqmp_dpsub_drm_cleanup(dpsub);
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else
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drm_bridge_remove(dpsub->bridge);
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zynqmp_disp_remove(dpsub);
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zynqmp_dp_remove(dpsub);
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pm_runtime_disable(&pdev->dev);
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clk_disable_unprepare(dpsub->apb_clk);
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of_reserved_mem_device_release(&pdev->dev);
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if (!dpsub->drm)
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zynqmp_dpsub_release(dpsub);
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return 0;
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}
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static void zynqmp_dpsub_shutdown(struct platform_device *pdev)
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{
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struct zynqmp_dpsub *dpsub = platform_get_drvdata(pdev);
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if (!dpsub->drm)
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return;
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drm_atomic_helper_shutdown(&dpsub->drm->dev);
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}
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static const struct of_device_id zynqmp_dpsub_of_match[] = {
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{ .compatible = "xlnx,zynqmp-dpsub-1.7", },
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{ /* end of table */ },
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};
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MODULE_DEVICE_TABLE(of, zynqmp_dpsub_of_match);
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static struct platform_driver zynqmp_dpsub_driver = {
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.probe = zynqmp_dpsub_probe,
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.remove = zynqmp_dpsub_remove,
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.shutdown = zynqmp_dpsub_shutdown,
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.driver = {
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.name = "zynqmp-dpsub",
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.pm = &zynqmp_dpsub_pm_ops,
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.of_match_table = zynqmp_dpsub_of_match,
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},
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};
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drm_module_platform_driver(zynqmp_dpsub_driver);
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MODULE_AUTHOR("Xilinx, Inc.");
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MODULE_DESCRIPTION("ZynqMP DP Subsystem Driver");
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MODULE_LICENSE("GPL v2");
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