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51ae3bd4f0
To prepare for usage of the DPSUB as a DisplayPort bridge without creating a DRM device, make initialization and usage of the DMA engine optional. The flag that controls this feature is currently hardcoded to operating with the DMA engine, this will be made dynamic based on the device tree configuration in a subsequent change. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
86 lines
2.1 KiB
C
86 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ZynqMP DPSUB Subsystem Driver
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*
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* Copyright (C) 2017 - 2020 Xilinx, Inc.
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*
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* Authors:
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* - Hyun Woo Kwon <hyun.kwon@xilinx.com>
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* - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*/
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#ifndef _ZYNQMP_DPSUB_H_
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#define _ZYNQMP_DPSUB_H_
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struct clk;
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struct device;
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struct drm_bridge;
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struct zynqmp_disp;
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struct zynqmp_disp_layer;
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struct zynqmp_dp;
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struct zynqmp_dpsub_drm;
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#define ZYNQMP_DPSUB_NUM_LAYERS 2
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enum zynqmp_dpsub_port {
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ZYNQMP_DPSUB_PORT_LIVE_VIDEO,
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ZYNQMP_DPSUB_PORT_LIVE_GFX,
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ZYNQMP_DPSUB_PORT_LIVE_AUDIO,
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ZYNQMP_DPSUB_PORT_OUT_VIDEO,
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ZYNQMP_DPSUB_PORT_OUT_AUDIO,
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ZYNQMP_DPSUB_PORT_OUT_DP,
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ZYNQMP_DPSUB_NUM_PORTS,
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};
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enum zynqmp_dpsub_format {
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ZYNQMP_DPSUB_FORMAT_RGB,
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ZYNQMP_DPSUB_FORMAT_YCRCB444,
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ZYNQMP_DPSUB_FORMAT_YCRCB422,
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ZYNQMP_DPSUB_FORMAT_YONLY,
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};
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/**
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* struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem
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* @dev: The physical device
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* @apb_clk: The APB clock
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* @vid_clk: Video clock
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* @vid_clk_from_ps: True of the video clock comes from PS, false from PL
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* @aud_clk: Audio clock
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* @aud_clk_from_ps: True of the audio clock comes from PS, false from PL
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* @connected_ports: Bitmask of connected ports in the device tree
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* @dma_enabled: True if the DMA interface is enabled, false if the DPSUB is
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* driven by the live input
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* @drm: The DRM/KMS device data
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* @bridge: The DP encoder bridge
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* @disp: The display controller
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* @dp: The DisplayPort controller
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* @dma_align: DMA alignment constraint (must be a power of 2)
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*/
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struct zynqmp_dpsub {
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struct device *dev;
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struct clk *apb_clk;
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struct clk *vid_clk;
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bool vid_clk_from_ps;
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struct clk *aud_clk;
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bool aud_clk_from_ps;
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unsigned int connected_ports;
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bool dma_enabled;
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struct zynqmp_dpsub_drm *drm;
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struct drm_bridge *bridge;
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struct zynqmp_disp *disp;
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struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS];
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struct zynqmp_dp *dp;
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unsigned int dma_align;
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};
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bool zynqmp_dpsub_audio_enabled(struct zynqmp_dpsub *dpsub);
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unsigned int zynqmp_dpsub_get_audio_clk_rate(struct zynqmp_dpsub *dpsub);
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void zynqmp_dpsub_release(struct zynqmp_dpsub *dpsub);
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#endif /* _ZYNQMP_DPSUB_H_ */
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