Dave Jiang 7ed62bc344 cxl: Fix retrieving of access_coordinates in PCIe path ... [ Upstream commit 592780b839 ] Current loop in cxl_endpoint_get_perf_coordinates() incorrectly assumes the Root Port (RP) dport is the one with generic port access_coordinate. However those coordinates are one level up in the Host Bridge (HB). Current code causes the computation code to pick up 0s as the coordinates and cause minimal bandwidth to result in 0. Add check to skip RP when combining coordinates. Fixes: 14a6960b3e ("cxl: Add helper function that calculate performance data for downstream ports") Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://lore.kernel.org/r/20240403154844.3403859-3-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2024-04-17 11:23:30 +02:00
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Makefile	…
cdat.c	cxl: Split out host bridge access coordinates	2024-04-17 11:23:30 +02:00
core.h	…
hdm.c	…
mbox.c	cxl/core: Fix initialization of mbox_cmd.size_out in get event	2024-04-17 11:23:27 +02:00
memdev.c	cxl: Fix sysfs export of qos_class for memdev	2024-02-16 23:20:34 -08:00
pci.c	cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window	2024-02-16 23:20:34 -08:00
pmem.c	cxl: Refactor to use __free() for cxl_root allocation in cxl_find_nvdimm_bridge()	2024-01-05 14:36:29 -08:00
pmu.c	…
port.c	cxl: Fix retrieving of access_coordinates in PCIe path	2024-04-17 11:23:30 +02:00
region.c	cxl/region: Allow out of order assembly of autodiscovered regions	2024-02-16 23:20:34 -08:00
regs.c	cxl/core/regs: Fix usage of map->reg_type in cxl_decode_regblock() before assigned	2024-04-17 11:23:26 +02:00
suspend.c	…
trace.c	…
trace.h	cxl/trace: Properly initialize cxl_poison region name	2024-04-03 15:32:25 +02:00