1162 lines
33 KiB
C
1162 lines
33 KiB
C
/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "smu_types.h"
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#define SWSMU_CODE_LAYER_L2
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#include "amdgpu.h"
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#include "amdgpu_smu.h"
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#include "smu_v13_0.h"
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#include "smu13_driver_if_v13_0_4.h"
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#include "smu_v13_0_4_ppt.h"
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#include "smu_v13_0_4_ppsmc.h"
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#include "smu_v13_0_4_pmfw.h"
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#include "smu_cmn.h"
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/*
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* DO NOT use these for err/warn/info/debug messages.
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* Use dev_err, dev_warn, dev_info and dev_dbg instead.
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* They are more MGPU friendly.
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*/
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#undef pr_err
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#undef pr_warn
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#undef pr_info
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#undef pr_debug
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#define mmMP1_SMN_C2PMSG_66 0x0282
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#define mmMP1_SMN_C2PMSG_66_BASE_IDX 1
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#define mmMP1_SMN_C2PMSG_82 0x0292
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#define mmMP1_SMN_C2PMSG_82_BASE_IDX 1
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#define mmMP1_SMN_C2PMSG_90 0x029a
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#define mmMP1_SMN_C2PMSG_90_BASE_IDX 1
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#define FEATURE_MASK(feature) (1ULL << feature)
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#define SMU_13_0_4_UMD_PSTATE_GFXCLK 938
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#define SMU_13_0_4_UMD_PSTATE_SOCCLK 938
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#define SMU_13_0_4_UMD_PSTATE_FCLK 1875
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#define SMC_DPM_FEATURE ( \
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FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
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FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
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FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
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FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
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FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
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FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
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FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
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FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \
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FEATURE_MASK(FEATURE_ISP_DPM_BIT) | \
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FEATURE_MASK(FEATURE_IPU_DPM_BIT) | \
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FEATURE_MASK(FEATURE_GFX_DPM_BIT))
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static struct cmn2asic_msg_mapping smu_v13_0_4_message_map[SMU_MSG_MAX_COUNT] = {
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MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
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MSG_MAP(GetSmuVersion, PPSMC_MSG_GetPmfwVersion, 1),
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MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
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MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1),
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MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1),
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MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
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MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
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MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
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MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
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MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
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MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
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MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
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MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
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MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
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MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1),
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MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1),
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MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
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MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
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MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1),
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MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
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MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
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MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
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MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
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MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
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MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1),
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MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
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MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
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MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1),
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MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1),
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MSG_MAP(EnableGfxImu, PPSMC_MSG_EnableGfxImu, 1),
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MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1),
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MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1),
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};
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static struct cmn2asic_mapping smu_v13_0_4_feature_mask_map[SMU_FEATURE_COUNT] = {
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FEA_MAP(CCLK_DPM),
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FEA_MAP(FAN_CONTROLLER),
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FEA_MAP(PPT),
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FEA_MAP(TDC),
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FEA_MAP(THERMAL),
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FEA_MAP(VCN_DPM),
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FEA_MAP_REVERSE(FCLK),
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FEA_MAP_REVERSE(SOCCLK),
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FEA_MAP(LCLK_DPM),
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FEA_MAP(SHUBCLK_DPM),
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FEA_MAP(DCFCLK_DPM),
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FEA_MAP_HALF_REVERSE(GFX),
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FEA_MAP(DS_GFXCLK),
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FEA_MAP(DS_SOCCLK),
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FEA_MAP(DS_LCLK),
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FEA_MAP(DS_DCFCLK),
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FEA_MAP(DS_FCLK),
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FEA_MAP(DS_MP1CLK),
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FEA_MAP(DS_MP0CLK),
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FEA_MAP(GFX_DEM),
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FEA_MAP(PSI),
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FEA_MAP(PROCHOT),
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FEA_MAP(CPUOFF),
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FEA_MAP(STAPM),
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FEA_MAP(S0I3),
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FEA_MAP(PERF_LIMIT),
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FEA_MAP(CORE_DLDO),
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FEA_MAP(DS_VCN),
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FEA_MAP(CPPC),
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FEA_MAP(DF_CSTATES),
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FEA_MAP(ATHUB_PG),
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};
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static struct cmn2asic_mapping smu_v13_0_4_table_map[SMU_TABLE_COUNT] = {
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TAB_MAP_VALID(WATERMARKS),
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TAB_MAP_VALID(SMU_METRICS),
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TAB_MAP_VALID(CUSTOM_DPM),
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TAB_MAP_VALID(DPMCLOCKS),
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};
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static int smu_v13_0_4_init_smc_tables(struct smu_context *smu)
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{
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struct smu_table_context *smu_table = &smu->smu_table;
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struct smu_table *tables = smu_table->tables;
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SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
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SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
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SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
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smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
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if (!smu_table->clocks_table)
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goto err0_out;
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smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
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if (!smu_table->metrics_table)
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goto err1_out;
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smu_table->metrics_time = 0;
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smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
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if (!smu_table->watermarks_table)
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goto err2_out;
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smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
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smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
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if (!smu_table->gpu_metrics_table)
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goto err3_out;
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return 0;
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err3_out:
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kfree(smu_table->watermarks_table);
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err2_out:
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kfree(smu_table->metrics_table);
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err1_out:
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kfree(smu_table->clocks_table);
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err0_out:
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return -ENOMEM;
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}
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static int smu_v13_0_4_fini_smc_tables(struct smu_context *smu)
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{
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struct smu_table_context *smu_table = &smu->smu_table;
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kfree(smu_table->clocks_table);
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smu_table->clocks_table = NULL;
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kfree(smu_table->metrics_table);
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smu_table->metrics_table = NULL;
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kfree(smu_table->watermarks_table);
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smu_table->watermarks_table = NULL;
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kfree(smu_table->gpu_metrics_table);
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smu_table->gpu_metrics_table = NULL;
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return 0;
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}
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static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu)
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{
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int ret = 0;
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uint64_t feature_enabled;
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ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
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if (ret)
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return false;
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return !!(feature_enabled & SMC_DPM_FEATURE);
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}
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static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)
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{
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struct amdgpu_device *adev = smu->adev;
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int ret = 0;
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if (!en && !adev->in_s0ix) {
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/* Adds a GFX reset as workaround just before sending the
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* MP1_UNLOAD message to prevent GC/RLC/PMFW from entering
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* an invalid state.
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*/
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
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SMU_RESET_MODE_2, NULL);
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if (ret)
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return ret;
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ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
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}
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return ret;
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}
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static ssize_t smu_v13_0_4_get_gpu_metrics(struct smu_context *smu,
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void **table)
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{
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struct smu_table_context *smu_table = &smu->smu_table;
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struct gpu_metrics_v2_1 *gpu_metrics =
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(struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
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SmuMetrics_t metrics;
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int ret = 0;
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ret = smu_cmn_get_metrics_table(smu, &metrics, true);
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if (ret)
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return ret;
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smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
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gpu_metrics->temperature_gfx = metrics.GfxTemperature;
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gpu_metrics->temperature_soc = metrics.SocTemperature;
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memcpy(&gpu_metrics->temperature_core[0],
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&metrics.CoreTemperature[0],
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sizeof(uint16_t) * 8);
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gpu_metrics->temperature_l3[0] = metrics.L3Temperature;
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gpu_metrics->average_gfx_activity = metrics.GfxActivity;
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gpu_metrics->average_mm_activity = metrics.UvdActivity;
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gpu_metrics->average_socket_power = metrics.AverageSocketPower;
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gpu_metrics->average_gfx_power = metrics.Power[0];
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gpu_metrics->average_soc_power = metrics.Power[1];
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memcpy(&gpu_metrics->average_core_power[0],
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&metrics.CorePower[0],
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sizeof(uint16_t) * 8);
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gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
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gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
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gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
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gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
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gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
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gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
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memcpy(&gpu_metrics->current_coreclk[0],
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&metrics.CoreFrequency[0],
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sizeof(uint16_t) * 8);
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gpu_metrics->current_l3clk[0] = metrics.L3Frequency;
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gpu_metrics->throttle_status = metrics.ThrottlerStatus;
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gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
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*table = (void *)gpu_metrics;
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return sizeof(struct gpu_metrics_v2_1);
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}
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static int smu_v13_0_4_get_smu_metrics_data(struct smu_context *smu,
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MetricsMember_t member,
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uint32_t *value)
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{
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struct smu_table_context *smu_table = &smu->smu_table;
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SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
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int ret = 0;
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ret = smu_cmn_get_metrics_table(smu, NULL, false);
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if (ret)
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return ret;
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switch (member) {
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case METRICS_AVERAGE_GFXCLK:
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*value = metrics->GfxclkFrequency;
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break;
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case METRICS_AVERAGE_SOCCLK:
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*value = metrics->SocclkFrequency;
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break;
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case METRICS_AVERAGE_VCLK:
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*value = metrics->VclkFrequency;
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break;
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case METRICS_AVERAGE_DCLK:
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*value = metrics->DclkFrequency;
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break;
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case METRICS_AVERAGE_UCLK:
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*value = metrics->MemclkFrequency;
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break;
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case METRICS_AVERAGE_GFXACTIVITY:
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*value = metrics->GfxActivity / 100;
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break;
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case METRICS_AVERAGE_VCNACTIVITY:
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*value = metrics->UvdActivity;
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break;
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case METRICS_AVERAGE_SOCKETPOWER:
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*value = (metrics->AverageSocketPower << 8) / 1000;
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break;
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case METRICS_CURR_SOCKETPOWER:
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*value = (metrics->CurrentSocketPower << 8) / 1000;
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break;
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case METRICS_TEMPERATURE_EDGE:
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*value = metrics->GfxTemperature / 100 *
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SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
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break;
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case METRICS_TEMPERATURE_HOTSPOT:
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*value = metrics->SocTemperature / 100 *
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SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
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break;
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case METRICS_THROTTLER_STATUS:
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*value = metrics->ThrottlerStatus;
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break;
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case METRICS_VOLTAGE_VDDGFX:
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*value = metrics->Voltage[0];
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break;
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case METRICS_VOLTAGE_VDDSOC:
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*value = metrics->Voltage[1];
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break;
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case METRICS_SS_APU_SHARE:
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/* return the percentage of APU power with respect to APU's power limit.
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* percentage is reported, this isn't boost value. Smartshift power
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* boost/shift is only when the percentage is more than 100.
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*/
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if (metrics->StapmOpnLimit > 0)
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*value = (metrics->ApuPower * 100) / metrics->StapmOpnLimit;
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else
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*value = 0;
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break;
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case METRICS_SS_DGPU_SHARE:
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/* return the percentage of dGPU power with respect to dGPU's power limit.
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* percentage is reported, this isn't boost value. Smartshift power
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* boost/shift is only when the percentage is more than 100.
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*/
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if ((metrics->dGpuPower > 0) &&
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(metrics->StapmCurrentLimit > metrics->StapmOpnLimit))
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*value = (metrics->dGpuPower * 100) /
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(metrics->StapmCurrentLimit - metrics->StapmOpnLimit);
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else
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*value = 0;
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break;
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default:
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*value = UINT_MAX;
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break;
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}
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return ret;
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}
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static int smu_v13_0_4_get_current_clk_freq(struct smu_context *smu,
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enum smu_clk_type clk_type,
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uint32_t *value)
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{
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MetricsMember_t member_type;
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switch (clk_type) {
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case SMU_SOCCLK:
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member_type = METRICS_AVERAGE_SOCCLK;
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break;
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case SMU_VCLK:
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member_type = METRICS_AVERAGE_VCLK;
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break;
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case SMU_DCLK:
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member_type = METRICS_AVERAGE_DCLK;
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break;
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case SMU_MCLK:
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member_type = METRICS_AVERAGE_UCLK;
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break;
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case SMU_FCLK:
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return smu_cmn_send_smc_msg_with_param(smu,
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SMU_MSG_GetFclkFrequency,
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0, value);
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case SMU_GFXCLK:
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case SMU_SCLK:
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return smu_cmn_send_smc_msg_with_param(smu,
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SMU_MSG_GetGfxclkFrequency,
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0, value);
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break;
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default:
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return -EINVAL;
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}
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return smu_v13_0_4_get_smu_metrics_data(smu, member_type, value);
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}
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static int smu_v13_0_4_get_dpm_freq_by_index(struct smu_context *smu,
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enum smu_clk_type clk_type,
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uint32_t dpm_level,
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uint32_t *freq)
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{
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DpmClocks_t *clk_table = smu->smu_table.clocks_table;
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if (!clk_table || clk_type >= SMU_CLK_COUNT)
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return -EINVAL;
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switch (clk_type) {
|
|
case SMU_SOCCLK:
|
|
if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
|
|
return -EINVAL;
|
|
*freq = clk_table->SocClocks[dpm_level];
|
|
break;
|
|
case SMU_VCLK:
|
|
if (dpm_level >= clk_table->VcnClkLevelsEnabled)
|
|
return -EINVAL;
|
|
*freq = clk_table->VClocks[dpm_level];
|
|
break;
|
|
case SMU_DCLK:
|
|
if (dpm_level >= clk_table->VcnClkLevelsEnabled)
|
|
return -EINVAL;
|
|
*freq = clk_table->DClocks[dpm_level];
|
|
break;
|
|
case SMU_UCLK:
|
|
case SMU_MCLK:
|
|
if (dpm_level >= clk_table->NumDfPstatesEnabled)
|
|
return -EINVAL;
|
|
*freq = clk_table->DfPstateTable[dpm_level].MemClk;
|
|
break;
|
|
case SMU_FCLK:
|
|
if (dpm_level >= clk_table->NumDfPstatesEnabled)
|
|
return -EINVAL;
|
|
*freq = clk_table->DfPstateTable[dpm_level].FClk;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int smu_v13_0_4_get_dpm_level_count(struct smu_context *smu,
|
|
enum smu_clk_type clk_type,
|
|
uint32_t *count)
|
|
{
|
|
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
|
|
|
|
switch (clk_type) {
|
|
case SMU_SOCCLK:
|
|
*count = clk_table->NumSocClkLevelsEnabled;
|
|
break;
|
|
case SMU_VCLK:
|
|
*count = clk_table->VcnClkLevelsEnabled;
|
|
break;
|
|
case SMU_DCLK:
|
|
*count = clk_table->VcnClkLevelsEnabled;
|
|
break;
|
|
case SMU_MCLK:
|
|
*count = clk_table->NumDfPstatesEnabled;
|
|
break;
|
|
case SMU_FCLK:
|
|
*count = clk_table->NumDfPstatesEnabled;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int smu_v13_0_4_print_clk_levels(struct smu_context *smu,
|
|
enum smu_clk_type clk_type, char *buf)
|
|
{
|
|
int i, idx, size = 0, ret = 0;
|
|
uint32_t cur_value = 0, value = 0, count = 0;
|
|
uint32_t min, max;
|
|
|
|
smu_cmn_get_sysfs_buf(&buf, &size);
|
|
|
|
switch (clk_type) {
|
|
case SMU_OD_SCLK:
|
|
size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
|
|
size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
|
|
(smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
|
|
size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
|
|
(smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
|
|
break;
|
|
case SMU_OD_RANGE:
|
|
size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
|
|
size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
|
|
smu->gfx_default_hard_min_freq,
|
|
smu->gfx_default_soft_max_freq);
|
|
break;
|
|
case SMU_SOCCLK:
|
|
case SMU_VCLK:
|
|
case SMU_DCLK:
|
|
case SMU_MCLK:
|
|
case SMU_FCLK:
|
|
ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value);
|
|
if (ret)
|
|
break;
|
|
|
|
ret = smu_v13_0_4_get_dpm_level_count(smu, clk_type, &count);
|
|
if (ret)
|
|
break;
|
|
|
|
for (i = 0; i < count; i++) {
|
|
idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
|
|
ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, idx, &value);
|
|
if (ret)
|
|
break;
|
|
|
|
size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
|
|
cur_value == value ? "*" : "");
|
|
}
|
|
break;
|
|
case SMU_GFXCLK:
|
|
case SMU_SCLK:
|
|
ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value);
|
|
if (ret)
|
|
break;
|
|
min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
|
|
max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
|
|
if (cur_value == max)
|
|
i = 2;
|
|
else if (cur_value == min)
|
|
i = 0;
|
|
else
|
|
i = 1;
|
|
size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
|
|
i == 0 ? "*" : "");
|
|
size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
|
|
i == 1 ? cur_value : 1100, /* UMD PSTATE GFXCLK 1100 */
|
|
i == 1 ? "*" : "");
|
|
size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
|
|
i == 2 ? "*" : "");
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return size;
|
|
}
|
|
|
|
static int smu_v13_0_4_read_sensor(struct smu_context *smu,
|
|
enum amd_pp_sensors sensor,
|
|
void *data, uint32_t *size)
|
|
{
|
|
int ret = 0;
|
|
|
|
if (!data || !size)
|
|
return -EINVAL;
|
|
|
|
switch (sensor) {
|
|
case AMDGPU_PP_SENSOR_GPU_LOAD:
|
|
ret = smu_v13_0_4_get_smu_metrics_data(smu,
|
|
METRICS_AVERAGE_GFXACTIVITY,
|
|
(uint32_t *)data);
|
|
*size = 4;
|
|
break;
|
|
case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
|
|
ret = smu_v13_0_4_get_smu_metrics_data(smu,
|
|
METRICS_AVERAGE_SOCKETPOWER,
|
|
(uint32_t *)data);
|
|
*size = 4;
|
|
break;
|
|
case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
|
|
ret = smu_v13_0_4_get_smu_metrics_data(smu,
|
|
METRICS_CURR_SOCKETPOWER,
|
|
(uint32_t *)data);
|
|
*size = 4;
|
|
break;
|
|
case AMDGPU_PP_SENSOR_EDGE_TEMP:
|
|
ret = smu_v13_0_4_get_smu_metrics_data(smu,
|
|
METRICS_TEMPERATURE_EDGE,
|
|
(uint32_t *)data);
|
|
*size = 4;
|
|
break;
|
|
case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
|
|
ret = smu_v13_0_4_get_smu_metrics_data(smu,
|
|
METRICS_TEMPERATURE_HOTSPOT,
|
|
(uint32_t *)data);
|
|
*size = 4;
|
|
break;
|
|
case AMDGPU_PP_SENSOR_GFX_MCLK:
|
|
ret = smu_v13_0_4_get_smu_metrics_data(smu,
|
|
METRICS_AVERAGE_UCLK,
|
|
(uint32_t *)data);
|
|
*(uint32_t *)data *= 100;
|
|
*size = 4;
|
|
break;
|
|
case AMDGPU_PP_SENSOR_GFX_SCLK:
|
|
ret = smu_v13_0_4_get_smu_metrics_data(smu,
|
|
METRICS_AVERAGE_GFXCLK,
|
|
(uint32_t *)data);
|
|
*(uint32_t *)data *= 100;
|
|
*size = 4;
|
|
break;
|
|
case AMDGPU_PP_SENSOR_VDDGFX:
|
|
ret = smu_v13_0_4_get_smu_metrics_data(smu,
|
|
METRICS_VOLTAGE_VDDGFX,
|
|
(uint32_t *)data);
|
|
*size = 4;
|
|
break;
|
|
case AMDGPU_PP_SENSOR_VDDNB:
|
|
ret = smu_v13_0_4_get_smu_metrics_data(smu,
|
|
METRICS_VOLTAGE_VDDSOC,
|
|
(uint32_t *)data);
|
|
*size = 4;
|
|
break;
|
|
case AMDGPU_PP_SENSOR_SS_APU_SHARE:
|
|
ret = smu_v13_0_4_get_smu_metrics_data(smu,
|
|
METRICS_SS_APU_SHARE,
|
|
(uint32_t *)data);
|
|
*size = 4;
|
|
break;
|
|
case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
|
|
ret = smu_v13_0_4_get_smu_metrics_data(smu,
|
|
METRICS_SS_DGPU_SHARE,
|
|
(uint32_t *)data);
|
|
*size = 4;
|
|
break;
|
|
default:
|
|
ret = -EOPNOTSUPP;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int smu_v13_0_4_set_watermarks_table(struct smu_context *smu,
|
|
struct pp_smu_wm_range_sets *clock_ranges)
|
|
{
|
|
int i;
|
|
int ret = 0;
|
|
Watermarks_t *table = smu->smu_table.watermarks_table;
|
|
|
|
if (!table || !clock_ranges)
|
|
return -EINVAL;
|
|
|
|
if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
|
|
clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
|
|
return -EINVAL;
|
|
|
|
for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
|
|
table->WatermarkRow[WM_DCFCLK][i].MinClock =
|
|
clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
|
|
table->WatermarkRow[WM_DCFCLK][i].MaxClock =
|
|
clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
|
|
table->WatermarkRow[WM_DCFCLK][i].MinMclk =
|
|
clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
|
|
table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
|
|
clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
|
|
|
|
table->WatermarkRow[WM_DCFCLK][i].WmSetting =
|
|
clock_ranges->reader_wm_sets[i].wm_inst;
|
|
}
|
|
|
|
for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
|
|
table->WatermarkRow[WM_SOCCLK][i].MinClock =
|
|
clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
|
|
table->WatermarkRow[WM_SOCCLK][i].MaxClock =
|
|
clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
|
|
table->WatermarkRow[WM_SOCCLK][i].MinMclk =
|
|
clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
|
|
table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
|
|
clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
|
|
|
|
table->WatermarkRow[WM_SOCCLK][i].WmSetting =
|
|
clock_ranges->writer_wm_sets[i].wm_inst;
|
|
}
|
|
|
|
smu->watermarks_bitmap |= WATERMARKS_EXIST;
|
|
|
|
/* pass data to smu controller */
|
|
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
|
|
!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
|
|
ret = smu_cmn_write_watermarks_table(smu);
|
|
if (ret) {
|
|
dev_err(smu->adev->dev, "Failed to update WMTABLE!");
|
|
return ret;
|
|
}
|
|
smu->watermarks_bitmap |= WATERMARKS_LOADED;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool smu_v13_0_4_clk_dpm_is_enabled(struct smu_context *smu,
|
|
enum smu_clk_type clk_type)
|
|
{
|
|
enum smu_feature_mask feature_id = 0;
|
|
|
|
switch (clk_type) {
|
|
case SMU_MCLK:
|
|
case SMU_UCLK:
|
|
case SMU_FCLK:
|
|
feature_id = SMU_FEATURE_DPM_FCLK_BIT;
|
|
break;
|
|
case SMU_GFXCLK:
|
|
case SMU_SCLK:
|
|
feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
|
|
break;
|
|
case SMU_SOCCLK:
|
|
feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
|
|
break;
|
|
case SMU_VCLK:
|
|
case SMU_DCLK:
|
|
feature_id = SMU_FEATURE_VCN_DPM_BIT;
|
|
break;
|
|
default:
|
|
return true;
|
|
}
|
|
|
|
return smu_cmn_feature_is_enabled(smu, feature_id);
|
|
}
|
|
|
|
static int smu_v13_0_4_get_dpm_ultimate_freq(struct smu_context *smu,
|
|
enum smu_clk_type clk_type,
|
|
uint32_t *min,
|
|
uint32_t *max)
|
|
{
|
|
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
|
|
uint32_t clock_limit;
|
|
uint32_t max_dpm_level, min_dpm_level;
|
|
int ret = 0;
|
|
|
|
if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type)) {
|
|
switch (clk_type) {
|
|
case SMU_MCLK:
|
|
case SMU_UCLK:
|
|
clock_limit = smu->smu_table.boot_values.uclk;
|
|
break;
|
|
case SMU_FCLK:
|
|
clock_limit = smu->smu_table.boot_values.fclk;
|
|
break;
|
|
case SMU_GFXCLK:
|
|
case SMU_SCLK:
|
|
clock_limit = smu->smu_table.boot_values.gfxclk;
|
|
break;
|
|
case SMU_SOCCLK:
|
|
clock_limit = smu->smu_table.boot_values.socclk;
|
|
break;
|
|
case SMU_VCLK:
|
|
clock_limit = smu->smu_table.boot_values.vclk;
|
|
break;
|
|
case SMU_DCLK:
|
|
clock_limit = smu->smu_table.boot_values.dclk;
|
|
break;
|
|
default:
|
|
clock_limit = 0;
|
|
break;
|
|
}
|
|
|
|
/* clock in Mhz unit */
|
|
if (min)
|
|
*min = clock_limit / 100;
|
|
if (max)
|
|
*max = clock_limit / 100;
|
|
|
|
return 0;
|
|
}
|
|
|
|
if (max) {
|
|
switch (clk_type) {
|
|
case SMU_GFXCLK:
|
|
case SMU_SCLK:
|
|
*max = clk_table->MaxGfxClk;
|
|
break;
|
|
case SMU_MCLK:
|
|
case SMU_UCLK:
|
|
case SMU_FCLK:
|
|
max_dpm_level = 0;
|
|
break;
|
|
case SMU_SOCCLK:
|
|
max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
|
|
break;
|
|
case SMU_VCLK:
|
|
case SMU_DCLK:
|
|
max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
|
|
ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type,
|
|
max_dpm_level,
|
|
max);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (min) {
|
|
switch (clk_type) {
|
|
case SMU_GFXCLK:
|
|
case SMU_SCLK:
|
|
*min = clk_table->MinGfxClk;
|
|
break;
|
|
case SMU_MCLK:
|
|
case SMU_UCLK:
|
|
case SMU_FCLK:
|
|
min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
|
|
break;
|
|
case SMU_SOCCLK:
|
|
min_dpm_level = 0;
|
|
break;
|
|
case SMU_VCLK:
|
|
case SMU_DCLK:
|
|
min_dpm_level = 0;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
|
|
ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type,
|
|
min_dpm_level,
|
|
min);
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int smu_v13_0_4_set_soft_freq_limited_range(struct smu_context *smu,
|
|
enum smu_clk_type clk_type,
|
|
uint32_t min,
|
|
uint32_t max)
|
|
{
|
|
enum smu_message_type msg_set_min, msg_set_max;
|
|
uint32_t min_clk = min;
|
|
uint32_t max_clk = max;
|
|
int ret = 0;
|
|
|
|
if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type))
|
|
return -EINVAL;
|
|
|
|
switch (clk_type) {
|
|
case SMU_GFXCLK:
|
|
case SMU_SCLK:
|
|
msg_set_min = SMU_MSG_SetHardMinGfxClk;
|
|
msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
|
|
break;
|
|
case SMU_FCLK:
|
|
msg_set_min = SMU_MSG_SetHardMinFclkByFreq;
|
|
msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq;
|
|
break;
|
|
case SMU_SOCCLK:
|
|
msg_set_min = SMU_MSG_SetHardMinSocclkByFreq;
|
|
msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq;
|
|
break;
|
|
case SMU_VCLK:
|
|
case SMU_DCLK:
|
|
msg_set_min = SMU_MSG_SetHardMinVcn;
|
|
msg_set_max = SMU_MSG_SetSoftMaxVcn;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (clk_type == SMU_VCLK) {
|
|
min_clk = min << SMU_13_VCLK_SHIFT;
|
|
max_clk = max << SMU_13_VCLK_SHIFT;
|
|
}
|
|
|
|
ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return smu_cmn_send_smc_msg_with_param(smu, msg_set_max,
|
|
max_clk, NULL);
|
|
}
|
|
|
|
static int smu_v13_0_4_force_clk_levels(struct smu_context *smu,
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enum smu_clk_type clk_type,
|
|
uint32_t mask)
|
|
{
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|
uint32_t soft_min_level = 0, soft_max_level = 0;
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uint32_t min_freq = 0, max_freq = 0;
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int ret = 0;
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|
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soft_min_level = mask ? (ffs(mask) - 1) : 0;
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soft_max_level = mask ? (fls(mask) - 1) : 0;
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|
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|
switch (clk_type) {
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case SMU_SOCCLK:
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|
case SMU_FCLK:
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|
case SMU_VCLK:
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|
case SMU_DCLK:
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|
ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
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|
if (ret)
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|
break;
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|
|
|
ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
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if (ret)
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|
break;
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|
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ret = smu_v13_0_4_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
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break;
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default:
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|
ret = -EINVAL;
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|
break;
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|
}
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|
|
|
return ret;
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|
}
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|
|
|
static int smu_v13_0_4_get_dpm_profile_freq(struct smu_context *smu,
|
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enum amd_dpm_forced_level level,
|
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enum smu_clk_type clk_type,
|
|
uint32_t *min_clk,
|
|
uint32_t *max_clk)
|
|
{
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|
int ret = 0;
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uint32_t clk_limit = 0;
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|
|
|
switch (clk_type) {
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case SMU_GFXCLK:
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|
case SMU_SCLK:
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|
clk_limit = SMU_13_0_4_UMD_PSTATE_GFXCLK;
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if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
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smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
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else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
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|
break;
|
|
case SMU_SOCCLK:
|
|
clk_limit = SMU_13_0_4_UMD_PSTATE_SOCCLK;
|
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if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
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smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &clk_limit);
|
|
break;
|
|
case SMU_FCLK:
|
|
clk_limit = SMU_13_0_4_UMD_PSTATE_FCLK;
|
|
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
|
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smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit);
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else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
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smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &clk_limit, NULL);
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|
break;
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case SMU_VCLK:
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smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);
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|
break;
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case SMU_DCLK:
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);
|
|
break;
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|
default:
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|
ret = -EINVAL;
|
|
break;
|
|
}
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|
*min_clk = *max_clk = clk_limit;
|
|
return ret;
|
|
}
|
|
|
|
static int smu_v13_0_4_set_performance_level(struct smu_context *smu,
|
|
enum amd_dpm_forced_level level)
|
|
{
|
|
struct amdgpu_device *adev = smu->adev;
|
|
uint32_t sclk_min = 0, sclk_max = 0;
|
|
uint32_t fclk_min = 0, fclk_max = 0;
|
|
uint32_t socclk_min = 0, socclk_max = 0;
|
|
uint32_t vclk_min = 0, vclk_max = 0;
|
|
uint32_t dclk_min = 0, dclk_max = 0;
|
|
int ret = 0;
|
|
|
|
switch (level) {
|
|
case AMD_DPM_FORCED_LEVEL_HIGH:
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max);
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max);
|
|
sclk_min = sclk_max;
|
|
fclk_min = fclk_max;
|
|
socclk_min = socclk_max;
|
|
vclk_min = vclk_max;
|
|
dclk_min = dclk_max;
|
|
break;
|
|
case AMD_DPM_FORCED_LEVEL_LOW:
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL);
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL);
|
|
sclk_max = sclk_min;
|
|
fclk_max = fclk_min;
|
|
socclk_max = socclk_min;
|
|
vclk_max = vclk_min;
|
|
dclk_max = dclk_min;
|
|
break;
|
|
case AMD_DPM_FORCED_LEVEL_AUTO:
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max);
|
|
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max);
|
|
break;
|
|
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
|
|
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
|
|
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
|
|
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
|
|
smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);
|
|
smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_FCLK, &fclk_min, &fclk_max);
|
|
smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SOCCLK, &socclk_min, &socclk_max);
|
|
smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);
|
|
smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);
|
|
break;
|
|
case AMD_DPM_FORCED_LEVEL_MANUAL:
|
|
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
|
|
return 0;
|
|
default:
|
|
dev_err(adev->dev, "Invalid performance level %d\n", level);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (sclk_min && sclk_max) {
|
|
ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
|
|
SMU_SCLK,
|
|
sclk_min,
|
|
sclk_max);
|
|
if (ret)
|
|
return ret;
|
|
|
|
smu->gfx_actual_hard_min_freq = sclk_min;
|
|
smu->gfx_actual_soft_max_freq = sclk_max;
|
|
}
|
|
|
|
if (fclk_min && fclk_max) {
|
|
ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
|
|
SMU_FCLK,
|
|
fclk_min,
|
|
fclk_max);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (socclk_min && socclk_max) {
|
|
ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
|
|
SMU_SOCCLK,
|
|
socclk_min,
|
|
socclk_max);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (vclk_min && vclk_max) {
|
|
ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
|
|
SMU_VCLK,
|
|
vclk_min,
|
|
vclk_max);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (dclk_min && dclk_max) {
|
|
ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
|
|
SMU_DCLK,
|
|
dclk_min,
|
|
dclk_max);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int smu_v13_0_4_mode2_reset(struct smu_context *smu)
|
|
{
|
|
return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
|
|
SMU_RESET_MODE_2, NULL);
|
|
}
|
|
|
|
static int smu_v13_0_4_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
|
|
{
|
|
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
|
|
|
|
smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
|
|
smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
|
|
smu->gfx_actual_hard_min_freq = 0;
|
|
smu->gfx_actual_soft_max_freq = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pptable_funcs smu_v13_0_4_ppt_funcs = {
|
|
.check_fw_status = smu_v13_0_check_fw_status,
|
|
.check_fw_version = smu_v13_0_check_fw_version,
|
|
.init_smc_tables = smu_v13_0_4_init_smc_tables,
|
|
.fini_smc_tables = smu_v13_0_4_fini_smc_tables,
|
|
.get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
|
|
.system_features_control = smu_v13_0_4_system_features_control,
|
|
.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
|
|
.send_smc_msg = smu_cmn_send_smc_msg,
|
|
.dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
|
|
.dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
|
|
.set_default_dpm_table = smu_v13_0_set_default_dpm_tables,
|
|
.read_sensor = smu_v13_0_4_read_sensor,
|
|
.is_dpm_running = smu_v13_0_4_is_dpm_running,
|
|
.set_watermarks_table = smu_v13_0_4_set_watermarks_table,
|
|
.get_gpu_metrics = smu_v13_0_4_get_gpu_metrics,
|
|
.get_enabled_mask = smu_cmn_get_enabled_mask,
|
|
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
|
|
.set_driver_table_location = smu_v13_0_set_driver_table_location,
|
|
.gfx_off_control = smu_v13_0_gfx_off_control,
|
|
.mode2_reset = smu_v13_0_4_mode2_reset,
|
|
.get_dpm_ultimate_freq = smu_v13_0_4_get_dpm_ultimate_freq,
|
|
.od_edit_dpm_table = smu_v13_0_od_edit_dpm_table,
|
|
.print_clk_levels = smu_v13_0_4_print_clk_levels,
|
|
.force_clk_levels = smu_v13_0_4_force_clk_levels,
|
|
.set_performance_level = smu_v13_0_4_set_performance_level,
|
|
.set_fine_grain_gfx_freq_parameters = smu_v13_0_4_set_fine_grain_gfx_freq_parameters,
|
|
.set_gfx_power_up_by_imu = smu_v13_0_set_gfx_power_up_by_imu,
|
|
};
|
|
|
|
static void smu_v13_0_4_set_smu_mailbox_registers(struct smu_context *smu)
|
|
{
|
|
struct amdgpu_device *adev = smu->adev;
|
|
|
|
smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
|
|
smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
|
|
smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
|
|
}
|
|
|
|
void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu)
|
|
{
|
|
struct amdgpu_device *adev = smu->adev;
|
|
|
|
smu->ppt_funcs = &smu_v13_0_4_ppt_funcs;
|
|
smu->message_map = smu_v13_0_4_message_map;
|
|
smu->feature_map = smu_v13_0_4_feature_mask_map;
|
|
smu->table_map = smu_v13_0_4_table_map;
|
|
smu->smc_driver_if_version = SMU13_0_4_DRIVER_IF_VERSION;
|
|
smu->is_apu = true;
|
|
|
|
if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 4))
|
|
smu_v13_0_4_set_smu_mailbox_registers(smu);
|
|
else
|
|
smu_v13_0_set_smu_mailbox_registers(smu);
|
|
}
|