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0659452dd2
DRA7xx SoC has the same l3-noc interconnect ip (as OMAP4 and OMAP5), but AM437x SoC has just 2 modules instead of 3 which other SoCs have. So, stop using direct access of array indices and use of->match data and simplify implementation to benefit future usage. While at it, rename a few very generic variables to make them omap specific. This helps us differentiate from DRA7 and AM43xx data in the future. NOTE: None of the platforms that use omap_l3_noc are non-device tree anymore. So, it is safe to assume OF match here. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: split, refactor and optimize logic] Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Darren Etheridge <detheridge@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com>
185 lines
4.5 KiB
C
185 lines
4.5 KiB
C
/*
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* OMAP L3 Interconnect error handling driver header
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*
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* Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* sricharan <r.sricharan@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __OMAP_L3_NOC_H
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#define __OMAP_L3_NOC_H
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#define OMAP_L3_MODULES 3
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#define MAX_L3_MODULES 3
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#define CLEAR_STDERR_LOG (1 << 31)
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#define CUSTOM_ERROR 0x2
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#define STANDARD_ERROR 0x0
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#define INBAND_ERROR 0x0
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#define L3_APPLICATION_ERROR 0x0
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#define L3_DEBUG_ERROR 0x1
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/* L3 TARG register offsets */
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#define L3_TARG_STDERRLOG_MAIN 0x48
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#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
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#define L3_TARG_STDERRLOG_MSTADDR 0x68
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#define L3_FLAGMUX_REGERR0 0xc
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#define L3_FLAGMUX_MASK0 0x8
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#define L3_TARGET_NOT_SUPPORTED NULL
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#define MAX_CLKDM_TARGETS 31
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/**
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* struct l3_masters_data - L3 Master information
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* @id: ID of the L3 Master
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* @name: master name
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*/
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struct l3_masters_data {
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u32 id;
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char *name;
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};
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/**
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* struct l3_target_data - L3 Target information
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* @offset: Offset from base for L3 Target
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* @name: Target name
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*
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* Target information is organized indexed by bit field definitions.
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*/
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struct l3_target_data {
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u32 offset;
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char *name;
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};
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/**
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* struct omap_l3 - Description of data relevant for L3 bus.
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* @dev: device representing the bus (populated runtime)
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* @l3_base: base addresses of modules (populated runtime)
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* @l3_flag_mux: array containing offsets to flag mux per module
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* offset from corresponding module base indexed per
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* module.
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* @num_modules: number of clock domains / modules.
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* @l3_masters: array pointing to master data containing name and register
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* offset for the master.
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* @num_master: number of masters
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* @l3_targ: array indexed by flagmux index (bit offset) pointing to the
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* target data. unsupported ones are marked with
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* L3_TARGET_NOT_SUPPORTED
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* @debug_irq: irq number of the debug interrupt (populated runtime)
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* @app_irq: irq number of the application interrupt (populated runtime)
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*/
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struct omap_l3 {
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struct device *dev;
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void __iomem *l3_base[MAX_L3_MODULES];
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u32 *l3_flagmux;
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int num_modules;
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struct l3_masters_data *l3_masters;
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int num_masters;
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struct l3_target_data **l3_targ;
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int debug_irq;
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int app_irq;
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};
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static u32 omap_l3_flagmux[OMAP_L3_MODULES] = {
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0x500,
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0x1000,
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0X0200
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};
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static struct l3_target_data omap_l3_target_data_clk1[MAX_CLKDM_TARGETS] = {
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{0x100, "DMM1",},
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{0x200, "DMM2",},
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{0x300, "ABE",},
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{0x400, "L4CFG",},
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{0x600, "CLK2PWRDISC",},
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{0x0, "HOSTCLK1",},
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{0x900, "L4WAKEUP",},
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};
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static struct l3_target_data omap_l3_target_data_clk2[MAX_CLKDM_TARGETS] = {
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{0x500, "CORTEXM3",},
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{0x300, "DSS",},
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{0x100, "GPMC",},
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{0x400, "ISS",},
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{0x700, "IVAHD",},
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{0xD00, "AES1",},
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{0x900, "L4PER0",},
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{0x200, "OCMRAM",},
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{0x100, "GPMCsERROR",},
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{0x600, "SGX",},
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{0x800, "SL2",},
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{0x1600, "C2C",},
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{0x1100, "PWRDISCCLK1",},
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{0xF00, "SHA1",},
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{0xE00, "AES2",},
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{0xC00, "L4PER3",},
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{0xA00, "L4PER1",},
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{0xB00, "L4PER2",},
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{0x0, "HOSTCLK2",},
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{0x1800, "CAL",},
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{0x1700, "LLI",},
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};
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static struct l3_target_data omap_l3_target_data_clk3[MAX_CLKDM_TARGETS] = {
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{0x0100, "EMUSS",},
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{0x0300, "DEBUG SOURCE",},
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{0x0, "HOST CLK3",},
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};
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static struct l3_masters_data omap_l3_masters[] = {
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{ 0x0 , "MPU"},
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{ 0x10, "CS_ADP"},
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{ 0x14, "xxx"},
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{ 0x20, "DSP"},
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{ 0x30, "IVAHD"},
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{ 0x40, "ISS"},
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{ 0x44, "DucatiM3"},
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{ 0x48, "FaceDetect"},
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{ 0x50, "SDMA_Rd"},
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{ 0x54, "SDMA_Wr"},
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{ 0x58, "xxx"},
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{ 0x5C, "xxx"},
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{ 0x60, "SGX"},
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{ 0x70, "DSS"},
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{ 0x80, "C2C"},
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{ 0x88, "xxx"},
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{ 0x8C, "xxx"},
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{ 0x90, "HSI"},
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{ 0xA0, "MMC1"},
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{ 0xA4, "MMC2"},
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{ 0xA8, "MMC6"},
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{ 0xB0, "UNIPRO1"},
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{ 0xC0, "USBHOSTHS"},
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{ 0xC4, "USBOTGHS"},
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{ 0xC8, "USBHOSTFS"}
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};
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static struct l3_target_data *omap_l3_targ[OMAP_L3_MODULES] = {
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omap_l3_target_data_clk1,
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omap_l3_target_data_clk2,
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omap_l3_target_data_clk3,
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};
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static const struct omap_l3 omap_l3_data = {
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.l3_flagmux = omap_l3_flagmux,
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.num_modules = OMAP_L3_MODULES,
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.l3_masters = omap_l3_masters,
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.num_masters = ARRAY_SIZE(omap_l3_masters),
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.l3_targ = omap_l3_targ,
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};
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#endif /* __OMAP_L3_NOC_H */
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