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![Vasyl Gomonovych](/assets/img/avatar_default.png)
drivers/irqchip/irq-imgpdc.c:327:20-23: WARNING: Suspicious code. resource_size is maybe missing with res_regs Generated by: scripts/coccinelle/api/resource_size.cocci Signed-off-by: Vasyl Gomonovych <gomonovych@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: marc.zyngier@arm.com Cc: jason@lakedaemon.net Link: https://lkml.kernel.org/r/1511215361-8279-1-git-send-email-gomonovych@gmail.com
501 lines
13 KiB
C
501 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* IMG PowerDown Controller (PDC)
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*
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* Copyright 2010-2013 Imagination Technologies Ltd.
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*
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* Exposes the syswake and PDC peripheral wake interrupts to the system.
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*
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*/
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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/* PDC interrupt register numbers */
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#define PDC_IRQ_STATUS 0x310
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#define PDC_IRQ_ENABLE 0x314
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#define PDC_IRQ_CLEAR 0x318
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#define PDC_IRQ_ROUTE 0x31c
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#define PDC_SYS_WAKE_BASE 0x330
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#define PDC_SYS_WAKE_STRIDE 0x8
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#define PDC_SYS_WAKE_CONFIG_BASE 0x334
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#define PDC_SYS_WAKE_CONFIG_STRIDE 0x8
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/* PDC interrupt register field masks */
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#define PDC_IRQ_SYS3 0x08
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#define PDC_IRQ_SYS2 0x04
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#define PDC_IRQ_SYS1 0x02
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#define PDC_IRQ_SYS0 0x01
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#define PDC_IRQ_ROUTE_WU_EN_SYS3 0x08000000
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#define PDC_IRQ_ROUTE_WU_EN_SYS2 0x04000000
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#define PDC_IRQ_ROUTE_WU_EN_SYS1 0x02000000
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#define PDC_IRQ_ROUTE_WU_EN_SYS0 0x01000000
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#define PDC_IRQ_ROUTE_WU_EN_WD 0x00040000
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#define PDC_IRQ_ROUTE_WU_EN_IR 0x00020000
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#define PDC_IRQ_ROUTE_WU_EN_RTC 0x00010000
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#define PDC_IRQ_ROUTE_EXT_EN_SYS3 0x00000800
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#define PDC_IRQ_ROUTE_EXT_EN_SYS2 0x00000400
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#define PDC_IRQ_ROUTE_EXT_EN_SYS1 0x00000200
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#define PDC_IRQ_ROUTE_EXT_EN_SYS0 0x00000100
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#define PDC_IRQ_ROUTE_EXT_EN_WD 0x00000004
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#define PDC_IRQ_ROUTE_EXT_EN_IR 0x00000002
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#define PDC_IRQ_ROUTE_EXT_EN_RTC 0x00000001
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#define PDC_SYS_WAKE_RESET 0x00000010
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#define PDC_SYS_WAKE_INT_MODE 0x0000000e
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#define PDC_SYS_WAKE_INT_MODE_SHIFT 1
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#define PDC_SYS_WAKE_PIN_VAL 0x00000001
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/* PDC interrupt constants */
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#define PDC_SYS_WAKE_INT_LOW 0x0
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#define PDC_SYS_WAKE_INT_HIGH 0x1
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#define PDC_SYS_WAKE_INT_DOWN 0x2
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#define PDC_SYS_WAKE_INT_UP 0x3
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#define PDC_SYS_WAKE_INT_CHANGE 0x6
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#define PDC_SYS_WAKE_INT_NONE 0x4
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/**
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* struct pdc_intc_priv - private pdc interrupt data.
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* @nr_perips: Number of peripheral interrupt signals.
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* @nr_syswakes: Number of syswake signals.
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* @perip_irqs: List of peripheral IRQ numbers handled.
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* @syswake_irq: Shared PDC syswake IRQ number.
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* @domain: IRQ domain for PDC peripheral and syswake IRQs.
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* @pdc_base: Base of PDC registers.
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* @irq_route: Cached version of PDC_IRQ_ROUTE register.
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* @lock: Lock to protect the PDC syswake registers and the cached
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* values of those registers in this struct.
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*/
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struct pdc_intc_priv {
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unsigned int nr_perips;
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unsigned int nr_syswakes;
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unsigned int *perip_irqs;
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unsigned int syswake_irq;
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struct irq_domain *domain;
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void __iomem *pdc_base;
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u32 irq_route;
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raw_spinlock_t lock;
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};
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static void pdc_write(struct pdc_intc_priv *priv, unsigned int reg_offs,
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unsigned int data)
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{
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iowrite32(data, priv->pdc_base + reg_offs);
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}
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static unsigned int pdc_read(struct pdc_intc_priv *priv,
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unsigned int reg_offs)
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{
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return ioread32(priv->pdc_base + reg_offs);
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}
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/* Generic IRQ callbacks */
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#define SYS0_HWIRQ 8
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static unsigned int hwirq_is_syswake(irq_hw_number_t hw)
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{
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return hw >= SYS0_HWIRQ;
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}
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static unsigned int hwirq_to_syswake(irq_hw_number_t hw)
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{
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return hw - SYS0_HWIRQ;
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}
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static irq_hw_number_t syswake_to_hwirq(unsigned int syswake)
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{
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return SYS0_HWIRQ + syswake;
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}
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static struct pdc_intc_priv *irqd_to_priv(struct irq_data *data)
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{
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return (struct pdc_intc_priv *)data->domain->host_data;
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}
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/*
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* perip_irq_mask() and perip_irq_unmask() use IRQ_ROUTE which also contains
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* wake bits, therefore we cannot use the generic irqchip mask callbacks as they
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* cache the mask.
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*/
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static void perip_irq_mask(struct irq_data *data)
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{
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struct pdc_intc_priv *priv = irqd_to_priv(data);
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raw_spin_lock(&priv->lock);
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priv->irq_route &= ~data->mask;
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pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
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raw_spin_unlock(&priv->lock);
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}
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static void perip_irq_unmask(struct irq_data *data)
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{
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struct pdc_intc_priv *priv = irqd_to_priv(data);
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raw_spin_lock(&priv->lock);
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priv->irq_route |= data->mask;
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pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
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raw_spin_unlock(&priv->lock);
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}
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static int syswake_irq_set_type(struct irq_data *data, unsigned int flow_type)
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{
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struct pdc_intc_priv *priv = irqd_to_priv(data);
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unsigned int syswake = hwirq_to_syswake(data->hwirq);
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unsigned int irq_mode;
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unsigned int soc_sys_wake_regoff, soc_sys_wake;
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/* translate to syswake IRQ mode */
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switch (flow_type) {
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case IRQ_TYPE_EDGE_BOTH:
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irq_mode = PDC_SYS_WAKE_INT_CHANGE;
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break;
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case IRQ_TYPE_EDGE_RISING:
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irq_mode = PDC_SYS_WAKE_INT_UP;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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irq_mode = PDC_SYS_WAKE_INT_DOWN;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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irq_mode = PDC_SYS_WAKE_INT_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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irq_mode = PDC_SYS_WAKE_INT_LOW;
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break;
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default:
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return -EINVAL;
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}
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raw_spin_lock(&priv->lock);
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/* set the IRQ mode */
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soc_sys_wake_regoff = PDC_SYS_WAKE_BASE + syswake*PDC_SYS_WAKE_STRIDE;
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soc_sys_wake = pdc_read(priv, soc_sys_wake_regoff);
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soc_sys_wake &= ~PDC_SYS_WAKE_INT_MODE;
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soc_sys_wake |= irq_mode << PDC_SYS_WAKE_INT_MODE_SHIFT;
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pdc_write(priv, soc_sys_wake_regoff, soc_sys_wake);
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/* and update the handler */
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irq_setup_alt_chip(data, flow_type);
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raw_spin_unlock(&priv->lock);
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return 0;
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}
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/* applies to both peripheral and syswake interrupts */
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static int pdc_irq_set_wake(struct irq_data *data, unsigned int on)
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{
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struct pdc_intc_priv *priv = irqd_to_priv(data);
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irq_hw_number_t hw = data->hwirq;
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unsigned int mask = (1 << 16) << hw;
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unsigned int dst_irq;
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raw_spin_lock(&priv->lock);
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if (on)
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priv->irq_route |= mask;
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else
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priv->irq_route &= ~mask;
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pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
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raw_spin_unlock(&priv->lock);
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/* control the destination IRQ wakeup too for standby mode */
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if (hwirq_is_syswake(hw))
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dst_irq = priv->syswake_irq;
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else
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dst_irq = priv->perip_irqs[hw];
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irq_set_irq_wake(dst_irq, on);
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return 0;
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}
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static void pdc_intc_perip_isr(struct irq_desc *desc)
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{
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unsigned int irq = irq_desc_get_irq(desc);
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struct pdc_intc_priv *priv;
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unsigned int i, irq_no;
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priv = (struct pdc_intc_priv *)irq_desc_get_handler_data(desc);
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/* find the peripheral number */
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for (i = 0; i < priv->nr_perips; ++i)
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if (irq == priv->perip_irqs[i])
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goto found;
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/* should never get here */
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return;
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found:
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/* pass on the interrupt */
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irq_no = irq_linear_revmap(priv->domain, i);
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generic_handle_irq(irq_no);
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}
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static void pdc_intc_syswake_isr(struct irq_desc *desc)
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{
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struct pdc_intc_priv *priv;
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unsigned int syswake, irq_no;
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unsigned int status;
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priv = (struct pdc_intc_priv *)irq_desc_get_handler_data(desc);
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status = pdc_read(priv, PDC_IRQ_STATUS) &
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pdc_read(priv, PDC_IRQ_ENABLE);
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status &= (1 << priv->nr_syswakes) - 1;
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for (syswake = 0; status; status >>= 1, ++syswake) {
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/* Has this sys_wake triggered? */
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if (!(status & 1))
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continue;
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irq_no = irq_linear_revmap(priv->domain,
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syswake_to_hwirq(syswake));
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generic_handle_irq(irq_no);
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}
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}
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static void pdc_intc_setup(struct pdc_intc_priv *priv)
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{
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int i;
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unsigned int soc_sys_wake_regoff;
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unsigned int soc_sys_wake;
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/*
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* Mask all syswake interrupts before routing, or we could receive an
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* interrupt before we're ready to handle it.
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*/
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pdc_write(priv, PDC_IRQ_ENABLE, 0);
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/*
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* Enable routing of all syswakes
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* Disable all wake sources
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*/
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priv->irq_route = ((PDC_IRQ_ROUTE_EXT_EN_SYS0 << priv->nr_syswakes) -
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PDC_IRQ_ROUTE_EXT_EN_SYS0);
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pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
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/* Initialise syswake IRQ */
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for (i = 0; i < priv->nr_syswakes; ++i) {
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/* set the IRQ mode to none */
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soc_sys_wake_regoff = PDC_SYS_WAKE_BASE + i*PDC_SYS_WAKE_STRIDE;
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soc_sys_wake = PDC_SYS_WAKE_INT_NONE
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<< PDC_SYS_WAKE_INT_MODE_SHIFT;
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pdc_write(priv, soc_sys_wake_regoff, soc_sys_wake);
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}
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}
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static int pdc_intc_probe(struct platform_device *pdev)
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{
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struct pdc_intc_priv *priv;
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struct device_node *node = pdev->dev.of_node;
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struct resource *res_regs;
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struct irq_chip_generic *gc;
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unsigned int i;
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int irq, ret;
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u32 val;
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if (!node)
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return -ENOENT;
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/* Get registers */
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res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res_regs == NULL) {
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dev_err(&pdev->dev, "cannot find registers resource\n");
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return -ENOENT;
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}
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/* Allocate driver data */
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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dev_err(&pdev->dev, "cannot allocate device data\n");
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return -ENOMEM;
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}
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raw_spin_lock_init(&priv->lock);
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platform_set_drvdata(pdev, priv);
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/* Ioremap the registers */
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priv->pdc_base = devm_ioremap(&pdev->dev, res_regs->start,
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resource_size(res_regs));
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if (!priv->pdc_base)
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return -EIO;
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/* Get number of peripherals */
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ret = of_property_read_u32(node, "num-perips", &val);
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if (ret) {
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dev_err(&pdev->dev, "No num-perips node property found\n");
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return -EINVAL;
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}
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if (val > SYS0_HWIRQ) {
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dev_err(&pdev->dev, "num-perips (%u) out of range\n", val);
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return -EINVAL;
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}
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priv->nr_perips = val;
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/* Get number of syswakes */
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ret = of_property_read_u32(node, "num-syswakes", &val);
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if (ret) {
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dev_err(&pdev->dev, "No num-syswakes node property found\n");
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return -EINVAL;
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}
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if (val > SYS0_HWIRQ) {
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dev_err(&pdev->dev, "num-syswakes (%u) out of range\n", val);
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return -EINVAL;
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}
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priv->nr_syswakes = val;
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/* Get peripheral IRQ numbers */
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priv->perip_irqs = devm_kzalloc(&pdev->dev, 4 * priv->nr_perips,
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GFP_KERNEL);
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if (!priv->perip_irqs) {
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dev_err(&pdev->dev, "cannot allocate perip IRQ list\n");
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return -ENOMEM;
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}
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for (i = 0; i < priv->nr_perips; ++i) {
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irq = platform_get_irq(pdev, 1 + i);
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if (irq < 0) {
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dev_err(&pdev->dev, "cannot find perip IRQ #%u\n", i);
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return irq;
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}
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priv->perip_irqs[i] = irq;
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}
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/* check if too many were provided */
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if (platform_get_irq(pdev, 1 + i) >= 0) {
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dev_err(&pdev->dev, "surplus perip IRQs detected\n");
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return -EINVAL;
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}
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/* Get syswake IRQ number */
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "cannot find syswake IRQ\n");
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return irq;
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}
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priv->syswake_irq = irq;
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/* Set up an IRQ domain */
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priv->domain = irq_domain_add_linear(node, 16, &irq_generic_chip_ops,
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priv);
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if (unlikely(!priv->domain)) {
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dev_err(&pdev->dev, "cannot add IRQ domain\n");
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return -ENOMEM;
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}
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/*
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* Set up 2 generic irq chips with 2 chip types.
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* The first one for peripheral irqs (only 1 chip type used)
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* The second one for syswake irqs (edge and level chip types)
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*/
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ret = irq_alloc_domain_generic_chips(priv->domain, 8, 2, "pdc",
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handle_level_irq, 0, 0,
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IRQ_GC_INIT_NESTED_LOCK);
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if (ret)
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goto err_generic;
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/* peripheral interrupt chip */
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gc = irq_get_domain_generic_chip(priv->domain, 0);
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gc->unused = ~(BIT(priv->nr_perips) - 1);
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gc->reg_base = priv->pdc_base;
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/*
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* IRQ_ROUTE contains wake bits, so we can't use the generic versions as
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* they cache the mask
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*/
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gc->chip_types[0].regs.mask = PDC_IRQ_ROUTE;
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gc->chip_types[0].chip.irq_mask = perip_irq_mask;
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gc->chip_types[0].chip.irq_unmask = perip_irq_unmask;
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gc->chip_types[0].chip.irq_set_wake = pdc_irq_set_wake;
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/* syswake interrupt chip */
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gc = irq_get_domain_generic_chip(priv->domain, 8);
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gc->unused = ~(BIT(priv->nr_syswakes) - 1);
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gc->reg_base = priv->pdc_base;
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/* edge interrupts */
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gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH;
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gc->chip_types[0].handler = handle_edge_irq;
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gc->chip_types[0].regs.ack = PDC_IRQ_CLEAR;
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gc->chip_types[0].regs.mask = PDC_IRQ_ENABLE;
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gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
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gc->chip_types[0].chip.irq_set_type = syswake_irq_set_type;
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gc->chip_types[0].chip.irq_set_wake = pdc_irq_set_wake;
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/* for standby we pass on to the shared syswake IRQ */
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gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
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/* level interrupts */
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gc->chip_types[1].type = IRQ_TYPE_LEVEL_MASK;
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gc->chip_types[1].handler = handle_level_irq;
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gc->chip_types[1].regs.ack = PDC_IRQ_CLEAR;
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gc->chip_types[1].regs.mask = PDC_IRQ_ENABLE;
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gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
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gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
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gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
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gc->chip_types[1].chip.irq_set_type = syswake_irq_set_type;
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gc->chip_types[1].chip.irq_set_wake = pdc_irq_set_wake;
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/* for standby we pass on to the shared syswake IRQ */
|
|
gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
|
|
|
|
/* Set up the hardware to enable interrupt routing */
|
|
pdc_intc_setup(priv);
|
|
|
|
/* Setup chained handlers for the peripheral IRQs */
|
|
for (i = 0; i < priv->nr_perips; ++i) {
|
|
irq = priv->perip_irqs[i];
|
|
irq_set_chained_handler_and_data(irq, pdc_intc_perip_isr,
|
|
priv);
|
|
}
|
|
|
|
/* Setup chained handler for the syswake IRQ */
|
|
irq_set_chained_handler_and_data(priv->syswake_irq,
|
|
pdc_intc_syswake_isr, priv);
|
|
|
|
dev_info(&pdev->dev,
|
|
"PDC IRQ controller initialised (%u perip IRQs, %u syswake IRQs)\n",
|
|
priv->nr_perips,
|
|
priv->nr_syswakes);
|
|
|
|
return 0;
|
|
err_generic:
|
|
irq_domain_remove(priv->domain);
|
|
return ret;
|
|
}
|
|
|
|
static int pdc_intc_remove(struct platform_device *pdev)
|
|
{
|
|
struct pdc_intc_priv *priv = platform_get_drvdata(pdev);
|
|
|
|
irq_domain_remove(priv->domain);
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id pdc_intc_match[] = {
|
|
{ .compatible = "img,pdc-intc" },
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver pdc_intc_driver = {
|
|
.driver = {
|
|
.name = "pdc-intc",
|
|
.of_match_table = pdc_intc_match,
|
|
},
|
|
.probe = pdc_intc_probe,
|
|
.remove = pdc_intc_remove,
|
|
};
|
|
|
|
static int __init pdc_intc_init(void)
|
|
{
|
|
return platform_driver_register(&pdc_intc_driver);
|
|
}
|
|
core_initcall(pdc_intc_init);
|