linux-stable/drivers/clk
Katsuhiro Suzuki 763a895aa4 clk: fractional-divider: check parent rate only if flag is set
[ Upstream commit d13501a2be ]

Custom approximation of fractional-divider may not need parent clock
rate checking. For example Rockchip SoCs work fine using grand parent
clock rate even if target rate is greater than parent.

This patch checks parent clock rate only if CLK_SET_RATE_PARENT flag
is set.

For detailed example, clock tree of Rockchip I2S audio hardware.
  - Clock rate of CPLL is 1.2GHz, GPLL is 491.52MHz.
  - i2s1_div is integer divider can divide N (N is 1~128).
    Input clock is CPLL or GPLL. Initial divider value is N = 1.
    Ex) PLL = CPLL, N = 10, i2s1_div output rate is
      CPLL / 10 = 1.2GHz / 10 = 120MHz
  - i2s1_frac is fractional divider can divide input to x/y, x and
    y are 16bit integer.

CPLL --> | selector | ---> i2s1_div -+--> | selector | --> I2S1 MCLK
GPLL --> |          | ,--------------'    |          |
                      `--> i2s1_frac ---> |          |

Clock mux system try to choose suitable one from i2s1_div and
i2s1_frac for master clock (MCLK) of I2S1.

Bad scenario as follows:
  - Try to set MCLK to 8.192MHz (32kHz audio replay)
    Candidate setting is
    - i2s1_div: GPLL / 60 = 8.192MHz
    i2s1_div candidate is exactly same as target clock rate, so mux
    choose this clock source. i2s1_div output rate is changed
    491.52MHz -> 8.192MHz

  - After that try to set to 11.2896MHz (44.1kHz audio replay)
    Candidate settings are
    - i2s1_div : CPLL / 107 = 11.214945MHz
    - i2s1_frac: i2s1_div   = 8.192MHz
      This is because clk_fd_round_rate() thinks target rate
      (11.2896MHz) is higher than parent rate (i2s1_div = 8.192MHz)
      and returns parent clock rate.

Above is current upstreamed behavior. Clock mux system choose
i2s1_div, but this clock rate is not acceptable for I2S driver, so
users cannot replay audio.

Expected behavior is:
  - Try to set master clock to 11.2896MHz (44.1kHz audio replay)
    Candidate settings are
    - i2s1_div : CPLL / 107          = 11.214945MHz
    - i2s1_frac: i2s1_div * 147/6400 = 11.2896MHz
                 Change i2s1_div to GPLL / 1 = 491.52MHz at same
                 time.

If apply this commit, clk_fd_round_rate() calls custom approximate
function of Rockchip even if target rate is higher than parent.
Custom function changes both grand parent (i2s1_div) and parent
(i2s_frac) settings at same time. Clock mux system can choose
i2s1_frac and audio works fine.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
[sboyd@kernel.org: Make function into a macro instead]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-04-05 22:33:03 +02:00
..
actions clk: actions: Add S700 SoC clock support 2018-07-25 16:40:54 -07:00
at91 clk: at91: Fix division by zero in PLL recalc_rate() 2018-11-21 09:19:16 +01:00
axis
axs10x
bcm treewide: devm_kzalloc() -> devm_kcalloc() 2018-06-12 16:19:22 -07:00
berlin This time we have a good set of changes to the core framework that do some 2018-06-09 12:06:24 -07:00
davinci ARM: 32-bit SoC platform updates 2018-08-23 13:44:43 -07:00
h8300 clk: h8300: pr_err() strings should end with newlines 2017-12-06 22:40:02 -08:00
hisilicon reset: hisilicon: fix potential NULL pointer dereference 2018-11-21 09:19:17 +01:00
imgtec clk: boston: fix possible memory leak in clk_boston_setup() 2019-02-12 19:46:58 +01:00
imx clk: imx6sl: ensure MMDC CH0 handshake is bypassed 2019-02-12 19:47:08 +01:00
ingenic clk: ingenic: Fix doc of ingenic_cgu_div_info 2019-03-23 20:10:03 +01:00
keystone clk: keystone: sci-clk: add support for dynamically probing clocks 2018-03-08 11:43:15 +02:00
loongson1
mediatek Merge branches 'clk-hisi-usb', 'clk-silent-bulk', 'clk-mtk-hdmi', 'clk-mtk-mali' and 'clk-imx6ul-ccosr' into clk-next 2018-06-04 12:27:40 -07:00
meson clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL 2019-02-12 19:47:01 +01:00
microchip
mmp clk: mmp: Off by one in mmp_clk_add() 2018-12-21 14:15:19 +01:00
mvebu clk: mvebu: Off by one bugs in cp110_of_clk_get() 2018-12-21 14:15:19 +01:00
mxs clk: mxs: make clk_ops const 2017-11-01 23:25:43 -07:00
nxp clk: lpc32xx: Set name of regmap_config 2018-03-19 14:35:16 -07:00
pistachio
pxa clk: pxa: export 32kHz PLL 2018-07-06 13:52:57 -07:00
qcom clk: qcom: gcc: Use active only source for CPUSS clocks 2019-03-13 14:02:27 -07:00
renesas clk: renesas: r9a06g032: Fix UART34567 clock rate 2018-11-27 16:13:01 +01:00
rockchip clk: rockchip: fix typo in rk3188 spdif_frac parent 2019-01-09 17:38:44 +01:00
samsung clk: samsung: exynos5: Fix kfree() of const memory on setting driver_override 2019-03-23 20:10:03 +01:00
sirf We have two changes to the core framework this time around. The first being a 2017-11-17 20:04:24 -08:00
socfpga clk: socfpga: stratix10: fix naming convention for the fixed-clocks 2019-01-31 08:14:34 +01:00
spear clk: spear: fix WDT clock definition on SPEAr600 2018-04-06 13:45:34 -07:00
sprd clk: sprd: add RTC gate for SC9860 2018-03-16 15:53:30 -07:00
st treewide: kzalloc() -> kcalloc() 2018-06-12 16:19:22 -07:00
sunxi treewide: kzalloc() -> kcalloc() 2018-06-12 16:19:22 -07:00
sunxi-ng clk: sunxi: A31: Fix wrong AHB gate number 2019-03-23 20:09:47 +01:00
tegra clk: tegra: dfll: Fix a potential Oop in remove() 2019-03-05 17:58:46 +01:00
ti clk: ti: Fix error handling in ti_clk_parse_divider_data() 2019-03-13 14:02:27 -07:00
uniphier clk: uniphier: Fix update register for CPU-gear 2019-03-23 20:10:03 +01:00
ux500 clk: ux500: Drop AB8540/9540 support 2018-03-23 09:36:11 -07:00
versatile clk: versatile: Remove WARNs in ->round_rate() 2018-03-16 15:31:16 -07:00
x86 clk: x86: Stop marking clocks as CLK_IS_CRITICAL 2018-09-17 18:47:58 -07:00
zte clk: move clock common macros out from vendor directories 2017-12-21 15:00:38 -08:00
zynq
clk-asm9260.c treewide: Use struct_size() for kmalloc()-family 2018-06-06 11:15:43 -07:00
clk-aspeed.c The new and exciting feature this time around is in the clk core. 2018-08-15 21:41:21 -07:00
clk-axi-clkgen.c clk: axi-clkgen: Round closest in round_rate() and recalc_rate() 2017-12-21 18:07:53 -08:00
clk-axm5516.c
clk-bulk.c clk: bulk: silently error out on EPROBE_DEFER 2018-05-15 15:16:13 -07:00
clk-cdce706.c
clk-cdce925.c clk: cdce925: remove redundant check for non-null parent_name 2017-11-13 17:44:15 -08:00
clk-clps711x.c treewide: Use struct_size() for kmalloc()-family 2018-06-06 11:15:43 -07:00
clk-composite.c
clk-conf.c
clk-cs2000-cp.c clk: cs2000-cp: convert to SPDX identifiers 2018-08-02 13:55:00 -07:00
clk-devres.c
clk-divider.c clk: divider: read-only divider can propagate rate change 2018-03-12 15:10:26 -07:00
clk-efm32gg.c treewide: Use struct_size() for kmalloc()-family 2018-06-06 11:15:43 -07:00
clk-fixed-factor.c clk: fixed-factor: fix of_node_get-put imbalance 2018-11-27 16:13:04 +01:00
clk-fixed-rate.c clk: fixed-rate: fix of_node_get-put imbalance 2018-11-27 16:13:00 +01:00
clk-fractional-divider.c clk: fractional-divider: check parent rate only if flag is set 2019-04-05 22:33:03 +02:00
clk-gate.c clk: gate: expose clk_gate_ops::is_enabled 2017-08-31 18:35:45 -07:00
clk-gemini.c treewide: Use struct_size() for kmalloc()-family 2018-06-06 11:15:43 -07:00
clk-gpio.c clk: clk-gpio: Allow GPIO to sleep in set/get_parent 2018-03-19 13:53:08 -07:00
clk-hi655x.c
clk-highbank.c
clk-hsdk-pll.c ARC: clk: fix spelling mistake: "configurarion" -> "configuration" 2017-11-13 17:44:26 -08:00
clk-max9485.c clk: Add driver for MAX9485 2018-07-06 13:44:06 -07:00
clk-max77686.c
clk-moxart.c
clk-multiplier.c
clk-mux.c clk: honor CLK_MUX_ROUND_CLOSEST in generic clk mux 2018-04-16 09:25:07 -07:00
clk-nomadik.c
clk-npcm7xx.c clk: npcm7xx: fix memory allocation 2018-08-28 15:12:59 -07:00
clk-nspire.c
clk-oxnas.c
clk-palmas.c
clk-pwm.c
clk-qoriq.c clk: qoriq: add more divider clocks support 2017-12-21 15:57:28 -08:00
clk-rk808.c
clk-s2mps11.c clk: s2mps11: Fix matching when built as module and DT node contains compatible 2018-11-21 09:19:16 +01:00
clk-scmi.c clk: scmi: Fix the rounding of clock rate 2018-08-02 13:43:48 -07:00
clk-scpi.c
clk-si514.c clk-si514, clk-si544: Implement prepare/unprepare/is_prepared operations 2018-06-29 10:59:40 -07:00
clk-si544.c clk-si514, clk-si544: Implement prepare/unprepare/is_prepared operations 2018-06-29 10:59:40 -07:00
clk-si570.c
clk-si5351.c clk: si5351: _si5351_clkout_reset_pll() can be static 2017-12-28 10:49:48 -08:00
clk-si5351.h
clk-stm32f4.c clk: stm32: Add clk entry for SDMMC2 on stm32F769 2018-03-19 13:46:07 -07:00
clk-stm32h7.c treewide: Use struct_size() for kmalloc()-family 2018-06-06 11:15:43 -07:00
clk-stm32mp1.c This time we have a good set of changes to the core framework that do some 2018-06-09 12:06:24 -07:00
clk-tango4.c License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
clk-twl6040.c clk: clk-twl6040: Fix imprecise external abort for pdmclk 2019-03-23 20:10:03 +01:00
clk-u300.c clk: clk-u300: Fix a typo in two comment lines 2017-11-13 17:39:43 -08:00
clk-versaclock5.c clk: vc5: Abort clock configuration without upstream clock 2019-03-05 17:58:46 +01:00
clk-vt8500.c
clk-wm831x.c clk: make clk_init_data const 2017-11-01 23:25:51 -07:00
clk-xgene.c clk: clk-xgene: Adjust six checks for null pointers 2017-11-13 17:40:03 -08:00
clk.c clk: sysfs: fix invalid JSON in clk_dump 2019-03-05 17:58:46 +01:00
clk.h clk: Move __clk_{get,put}() into private clk.h API 2018-01-04 15:13:29 -08:00
clkdev.c ARM: 8778/1: clkdev: don't call __of_clk_get_by_name() unnecessarily from clk_get() 2018-08-13 16:27:52 +01:00
Kconfig clk: Add driver for MAX9485 2018-07-06 13:44:06 -07:00
Makefile The new and exciting feature this time around is in the clk core. 2018-08-15 21:41:21 -07:00