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linux-stable/drivers/gpu
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Xia Yang 0689aad70d drm/nouveau/fifo/gk104: fix chid bit mask 
Fix the channel id bit mask in FIFO schedule timeout error handling.

FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000.
FIFO_ENGINE_STATUS_ID      is bit 11:0  thus 0x00000fff.

Signed-off-by: Xia Yang <xiay@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:30 +10:00
..
drm drm/nouveau/fifo/gk104: fix chid bit mask 2016-03-14 10:13:30 +10:00
host1x gpu: host1x: Set DMA ops on device creation 2016-03-04 16:24:57 +01:00
ipu-v3 Merge drm-fixes into drm-next. 2016-03-14 09:46:02 +10:00
vga vga_switcheroo: Add support for switching only the DDC 2016-02-09 11:21:07 +01:00
Makefile