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f5fe12b1ea
In order to prevent aliasing attacks on the branch predictor, invalidate the BTB or instruction cache on CPUs that are known to be affected when taking an abort on a address that is outside of a user task limit: Cortex A8, A9, A12, A17, A73, A75: flush BTB. Cortex A15, Brahma B15: invalidate icache. If the IBE bit is not set, then there is little point to enabling the workaround. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Boot-tested-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Tony Lindgren <tony@atomide.com>
48 lines
1.1 KiB
C
48 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_ARM_SYSTEM_MISC_H
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#define __ASM_ARM_SYSTEM_MISC_H
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#ifndef __ASSEMBLY__
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#include <linux/compiler.h>
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#include <linux/linkage.h>
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#include <linux/irqflags.h>
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#include <linux/reboot.h>
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#include <linux/percpu.h>
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extern void cpu_init(void);
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void soft_restart(unsigned long);
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extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
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extern void (*arm_pm_idle)(void);
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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typedef void (*harden_branch_predictor_fn_t)(void);
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DECLARE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn);
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static inline void harden_branch_predictor(void)
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{
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harden_branch_predictor_fn_t fn = per_cpu(harden_branch_predictor_fn,
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smp_processor_id());
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if (fn)
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fn();
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}
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#else
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#define harden_branch_predictor() do { } while (0)
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#endif
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#define UDBG_UNDEFINED (1 << 0)
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#define UDBG_SYSCALL (1 << 1)
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#define UDBG_BADABORT (1 << 2)
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#define UDBG_SEGV (1 << 3)
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#define UDBG_BUS (1 << 4)
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extern unsigned int user_debug;
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static inline int handle_guest_sea(phys_addr_t addr, unsigned int esr)
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{
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return -1;
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* __ASM_ARM_SYSTEM_MISC_H */
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