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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
77 lines
2 KiB
C
77 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* linux/amba/pl093.h
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*
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* Copyright (c) 2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* AMBA PL093 SSMC (synchronous static memory controller)
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* See DDI0236.pdf (r0p4) for more details
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*/
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#define SMB_BANK(x) ((x) * 0x20) /* each bank control set is 0x20 apart */
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/* Offsets for SMBxxxxRy registers */
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#define SMBIDCYR (0x00)
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#define SMBWSTRDR (0x04)
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#define SMBWSTWRR (0x08)
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#define SMBWSTOENR (0x0C)
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#define SMBWSTWENR (0x10)
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#define SMBCR (0x14)
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#define SMBSR (0x18)
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#define SMBWSTBRDR (0x1C)
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/* Masks for SMB registers */
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#define IDCY_MASK (0xf)
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#define WSTRD_MASK (0xf)
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#define WSTWR_MASK (0xf)
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#define WSTOEN_MASK (0xf)
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#define WSTWEN_MASK (0xf)
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/* Notes from datasheet:
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* WSTOEN <= WSTRD
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* WSTWEN <= WSTWR
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*
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* WSTOEN is not used with nWAIT
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*/
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/* SMBCR bit definitions */
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#define SMBCR_BIWRITEEN (1 << 21)
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#define SMBCR_ADDRVALIDWRITEEN (1 << 20)
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#define SMBCR_SYNCWRITE (1 << 17)
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#define SMBCR_BMWRITE (1 << 16)
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#define SMBCR_WRAPREAD (1 << 14)
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#define SMBCR_BIREADEN (1 << 13)
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#define SMBCR_ADDRVALIDREADEN (1 << 12)
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#define SMBCR_SYNCREAD (1 << 9)
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#define SMBCR_BMREAD (1 << 8)
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#define SMBCR_SMBLSPOL (1 << 6)
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#define SMBCR_WP (1 << 3)
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#define SMBCR_WAITEN (1 << 2)
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#define SMBCR_WAITPOL (1 << 1)
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#define SMBCR_RBLE (1 << 0)
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#define SMBCR_BURSTLENWRITE_MASK (3 << 18)
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#define SMBCR_BURSTLENWRITE_4 (0 << 18)
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#define SMBCR_BURSTLENWRITE_8 (1 << 18)
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#define SMBCR_BURSTLENWRITE_RESERVED (2 << 18)
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#define SMBCR_BURSTLENWRITE_CONTINUOUS (3 << 18)
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#define SMBCR_BURSTLENREAD_MASK (3 << 10)
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#define SMBCR_BURSTLENREAD_4 (0 << 10)
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#define SMBCR_BURSTLENREAD_8 (1 << 10)
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#define SMBCR_BURSTLENREAD_16 (2 << 10)
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#define SMBCR_BURSTLENREAD_CONTINUOUS (3 << 10)
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#define SMBCR_MW_MASK (3 << 4)
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#define SMBCR_MW_8BIT (0 << 4)
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#define SMBCR_MW_16BIT (1 << 4)
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#define SMBCR_MW_M32BIT (2 << 4)
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/* SSMC status registers */
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#define SSMCCSR (0x200)
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#define SSMCCR (0x204)
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#define SSMCITCR (0x208)
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#define SSMCITIP (0x20C)
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#define SSMCITIOP (0x210)
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