Tero Kristo 07ff73a932 clk: ti: omap5+: dpll: implement errata i810 ... Errata i810 states that DPLL controller can get stuck while transitioning to a power saving state, while its M/N ratio is being re-programmed. As a workaround, before re-programming the M/N ratio, SW has to ensure the DPLL cannot start an idle state transition. SW can disable DPLL idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request active by setting a dependent clock domain in SW_WKUP. This errata impacts OMAP5 and DRA7 chips, so enable the errata for these. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2015-11-30 11:34:17 -08:00
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at91_pmc.h	clk: at91: add generated clock driver	2015-10-01 12:48:11 -07:00
bcm2835.h
clk-conf.h	clk: Add missing header for 'bool' definition to clk-conf.h	2015-08-25 10:54:06 -07:00
mxs.h	ARM: mxs: remove custom .init_time hook	2013-09-29 21:09:34 +02:00
shmobile.h	clk: shmobile: Add CPG/MSTP Clock Domain support	2015-08-12 10:31:26 +09:00
tegra.h	clk: tegra: Properly include clk.h	2015-07-20 11:11:17 -07:00
ti.h	clk: ti: omap5+: dpll: implement errata i810	2015-11-30 11:34:17 -08:00
zynq.h	ARM: zynq: Map I/O memory on clkc init	2014-02-10 11:21:13 +01:00