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ae47ee5fc4
Evaluate the desired pixel clock polarity from the device tree. Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
18 lines
338 B
C
18 lines
338 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef MT9P031_H
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#define MT9P031_H
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struct v4l2_subdev;
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/*
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* struct mt9p031_platform_data - MT9P031 platform data
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* @ext_freq: Input clock frequency
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* @target_freq: Pixel clock frequency
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*/
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struct mt9p031_platform_data {
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unsigned int pixclk_pol:1;
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int ext_freq;
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int target_freq;
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};
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#endif
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