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![Ben Skeggs](/assets/img/avatar_default.png)
This class supports a WFI method (0x0078) that's not present on the KeplerChannelGpfifoA class. The binary driver exposes both classes on these GPUs for some reason, though there doesn't appear to be any difference in the setup that's done for each (ie. even if you allocate GpfifoA, the WFI method will still work). We shall just expose GpfifoB, as I don't see a good reason to report the presence of both. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
436 lines
12 KiB
C
436 lines
12 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <nvif/os.h>
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#include <nvif/class.h>
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#include <nvif/cl0002.h>
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#include <nvif/cl006b.h>
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#include <nvif/cl506f.h>
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#include <nvif/cl906f.h>
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#include <nvif/cla06f.h>
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#include <nvif/ioctl.h>
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/*XXX*/
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#include <core/client.h>
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#include "nouveau_drm.h"
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#include "nouveau_dma.h"
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#include "nouveau_bo.h"
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#include "nouveau_chan.h"
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#include "nouveau_fence.h"
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#include "nouveau_abi16.h"
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MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
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int nouveau_vram_pushbuf;
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module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
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int
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nouveau_channel_idle(struct nouveau_channel *chan)
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{
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if (likely(chan && chan->fence)) {
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struct nouveau_cli *cli = (void *)chan->user.client;
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struct nouveau_fence *fence = NULL;
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int ret;
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ret = nouveau_fence_new(chan, false, &fence);
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if (!ret) {
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ret = nouveau_fence_wait(fence, false, false);
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nouveau_fence_unref(&fence);
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}
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if (ret) {
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NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n",
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chan->chid, nvxx_client(&cli->base)->name);
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return ret;
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}
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}
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return 0;
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}
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void
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nouveau_channel_del(struct nouveau_channel **pchan)
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{
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struct nouveau_channel *chan = *pchan;
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if (chan) {
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if (chan->fence)
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nouveau_fence(chan->drm)->context_del(chan);
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nvif_object_fini(&chan->nvsw);
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nvif_object_fini(&chan->gart);
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nvif_object_fini(&chan->vram);
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nvif_object_fini(&chan->user);
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nvif_object_fini(&chan->push.ctxdma);
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nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma);
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nouveau_bo_unmap(chan->push.buffer);
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if (chan->push.buffer && chan->push.buffer->pin_refcnt)
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nouveau_bo_unpin(chan->push.buffer);
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nouveau_bo_ref(NULL, &chan->push.buffer);
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kfree(chan);
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}
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*pchan = NULL;
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}
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static int
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nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
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u32 size, struct nouveau_channel **pchan)
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{
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struct nouveau_cli *cli = (void *)device->object.client;
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struct nvkm_mmu *mmu = nvxx_mmu(device);
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struct nv_dma_v0 args = {};
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struct nouveau_channel *chan;
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u32 target;
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int ret;
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chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
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if (!chan)
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return -ENOMEM;
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chan->device = device;
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chan->drm = drm;
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/* allocate memory for dma push buffer */
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target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
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if (nouveau_vram_pushbuf)
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target = TTM_PL_FLAG_VRAM;
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ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, NULL,
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&chan->push.buffer);
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if (ret == 0) {
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ret = nouveau_bo_pin(chan->push.buffer, target, false);
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if (ret == 0)
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ret = nouveau_bo_map(chan->push.buffer);
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}
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if (ret) {
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nouveau_channel_del(pchan);
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return ret;
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}
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/* create dma object covering the *entire* memory space that the
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* pushbuf lives in, this is because the GEM code requires that
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* we be able to call out to other (indirect) push buffers
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*/
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chan->push.vma.offset = chan->push.buffer->bo.offset;
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if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
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ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm,
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&chan->push.vma);
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if (ret) {
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nouveau_channel_del(pchan);
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return ret;
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}
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args.target = NV_DMA_V0_TARGET_VM;
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args.access = NV_DMA_V0_ACCESS_VM;
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args.start = 0;
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args.limit = cli->vm->mmu->limit - 1;
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} else
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if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
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if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
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/* nv04 vram pushbuf hack, retarget to its location in
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* the framebuffer bar rather than direct vram access..
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* nfi why this exists, it came from the -nv ddx.
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*/
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args.target = NV_DMA_V0_TARGET_PCI;
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args.access = NV_DMA_V0_ACCESS_RDWR;
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args.start = nvxx_device(device)->func->
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resource_addr(nvxx_device(device), 1);
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args.limit = args.start + device->info.ram_user - 1;
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} else {
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args.target = NV_DMA_V0_TARGET_VRAM;
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args.access = NV_DMA_V0_ACCESS_RDWR;
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args.start = 0;
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args.limit = device->info.ram_user - 1;
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}
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} else {
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if (chan->drm->agp.bridge) {
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args.target = NV_DMA_V0_TARGET_AGP;
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args.access = NV_DMA_V0_ACCESS_RDWR;
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args.start = chan->drm->agp.base;
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args.limit = chan->drm->agp.base +
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chan->drm->agp.size - 1;
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} else {
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args.target = NV_DMA_V0_TARGET_VM;
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args.access = NV_DMA_V0_ACCESS_RDWR;
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args.start = 0;
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args.limit = mmu->limit - 1;
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}
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}
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ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
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&args, sizeof(args), &chan->push.ctxdma);
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if (ret) {
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nouveau_channel_del(pchan);
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return ret;
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}
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return 0;
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}
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static int
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nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
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u32 engine, struct nouveau_channel **pchan)
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{
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static const u16 oclasses[] = { MAXWELL_CHANNEL_GPFIFO_A,
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KEPLER_CHANNEL_GPFIFO_B,
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KEPLER_CHANNEL_GPFIFO_A,
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FERMI_CHANNEL_GPFIFO,
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G82_CHANNEL_GPFIFO,
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NV50_CHANNEL_GPFIFO,
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0 };
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const u16 *oclass = oclasses;
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union {
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struct nv50_channel_gpfifo_v0 nv50;
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struct fermi_channel_gpfifo_v0 fermi;
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struct kepler_channel_gpfifo_a_v0 kepler;
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} args;
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struct nouveau_channel *chan;
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u32 size;
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int ret;
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/* allocate dma push buffer */
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ret = nouveau_channel_prep(drm, device, 0x12000, &chan);
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*pchan = chan;
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if (ret)
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return ret;
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/* create channel object */
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do {
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if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) {
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args.kepler.version = 0;
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args.kepler.engines = engine;
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args.kepler.ilength = 0x02000;
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args.kepler.ioffset = 0x10000 + chan->push.vma.offset;
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args.kepler.vm = 0;
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size = sizeof(args.kepler);
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} else
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if (oclass[0] >= FERMI_CHANNEL_GPFIFO) {
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args.fermi.version = 0;
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args.fermi.ilength = 0x02000;
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args.fermi.ioffset = 0x10000 + chan->push.vma.offset;
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args.fermi.vm = 0;
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size = sizeof(args.fermi);
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} else {
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args.nv50.version = 0;
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args.nv50.ilength = 0x02000;
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args.nv50.ioffset = 0x10000 + chan->push.vma.offset;
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args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma);
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args.nv50.vm = 0;
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size = sizeof(args.nv50);
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}
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ret = nvif_object_init(&device->object, 0, *oclass++,
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&args, size, &chan->user);
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if (ret == 0) {
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if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A)
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chan->chid = args.kepler.chid;
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else
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if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO)
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chan->chid = args.fermi.chid;
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else
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chan->chid = args.nv50.chid;
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return ret;
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}
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} while (*oclass);
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nouveau_channel_del(pchan);
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return ret;
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}
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static int
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nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device,
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struct nouveau_channel **pchan)
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{
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static const u16 oclasses[] = { NV40_CHANNEL_DMA,
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NV17_CHANNEL_DMA,
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NV10_CHANNEL_DMA,
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NV03_CHANNEL_DMA,
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0 };
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const u16 *oclass = oclasses;
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struct nv03_channel_dma_v0 args;
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struct nouveau_channel *chan;
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int ret;
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/* allocate dma push buffer */
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ret = nouveau_channel_prep(drm, device, 0x10000, &chan);
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*pchan = chan;
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if (ret)
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return ret;
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/* create channel object */
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args.version = 0;
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args.pushbuf = nvif_handle(&chan->push.ctxdma);
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args.offset = chan->push.vma.offset;
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do {
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ret = nvif_object_init(&device->object, 0, *oclass++,
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&args, sizeof(args), &chan->user);
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if (ret == 0) {
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chan->chid = args.chid;
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return ret;
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}
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} while (ret && *oclass);
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nouveau_channel_del(pchan);
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return ret;
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}
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static int
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nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
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{
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struct nvif_device *device = chan->device;
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struct nouveau_cli *cli = (void *)chan->user.client;
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struct nvkm_mmu *mmu = nvxx_mmu(device);
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struct nv_dma_v0 args = {};
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int ret, i;
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nvif_object_map(&chan->user);
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/* allocate dma objects to cover all allowed vram, and gart */
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if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
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if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
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args.target = NV_DMA_V0_TARGET_VM;
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args.access = NV_DMA_V0_ACCESS_VM;
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args.start = 0;
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args.limit = cli->vm->mmu->limit - 1;
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} else {
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args.target = NV_DMA_V0_TARGET_VRAM;
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args.access = NV_DMA_V0_ACCESS_RDWR;
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args.start = 0;
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args.limit = device->info.ram_user - 1;
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}
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ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY,
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&args, sizeof(args), &chan->vram);
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if (ret)
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return ret;
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if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
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args.target = NV_DMA_V0_TARGET_VM;
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args.access = NV_DMA_V0_ACCESS_VM;
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args.start = 0;
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args.limit = cli->vm->mmu->limit - 1;
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} else
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if (chan->drm->agp.bridge) {
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args.target = NV_DMA_V0_TARGET_AGP;
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args.access = NV_DMA_V0_ACCESS_RDWR;
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args.start = chan->drm->agp.base;
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args.limit = chan->drm->agp.base +
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chan->drm->agp.size - 1;
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} else {
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args.target = NV_DMA_V0_TARGET_VM;
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args.access = NV_DMA_V0_ACCESS_RDWR;
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args.start = 0;
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args.limit = mmu->limit - 1;
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}
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ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY,
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&args, sizeof(args), &chan->gart);
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if (ret)
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return ret;
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}
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/* initialise dma tracking parameters */
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switch (chan->user.oclass & 0x00ff) {
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case 0x006b:
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case 0x006e:
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chan->user_put = 0x40;
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chan->user_get = 0x44;
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chan->dma.max = (0x10000 / 4) - 2;
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break;
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default:
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chan->user_put = 0x40;
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chan->user_get = 0x44;
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chan->user_get_hi = 0x60;
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chan->dma.ib_base = 0x10000 / 4;
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chan->dma.ib_max = (0x02000 / 8) - 1;
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chan->dma.ib_put = 0;
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chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
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chan->dma.max = chan->dma.ib_base;
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break;
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}
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chan->dma.put = 0;
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chan->dma.cur = chan->dma.put;
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chan->dma.free = chan->dma.max - chan->dma.cur;
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ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
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if (ret)
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return ret;
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for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
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OUT_RING(chan, 0x00000000);
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/* allocate software object class (used for fences on <= nv05) */
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if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
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ret = nvif_object_init(&chan->user, 0x006e,
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NVIF_CLASS_SW_NV04,
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NULL, 0, &chan->nvsw);
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if (ret)
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return ret;
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ret = RING_SPACE(chan, 2);
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if (ret)
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return ret;
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BEGIN_NV04(chan, NvSubSw, 0x0000, 1);
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OUT_RING (chan, chan->nvsw.handle);
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FIRE_RING (chan);
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}
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/* initialise synchronisation */
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return nouveau_fence(chan->drm)->context_new(chan);
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}
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int
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nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device,
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u32 arg0, u32 arg1, struct nouveau_channel **pchan)
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{
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struct nouveau_cli *cli = (void *)device->object.client;
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bool super;
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int ret;
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/* hack until fencenv50 is fixed, and agp access relaxed */
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super = cli->base.super;
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cli->base.super = true;
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ret = nouveau_channel_ind(drm, device, arg0, pchan);
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if (ret) {
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NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret);
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ret = nouveau_channel_dma(drm, device, pchan);
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if (ret) {
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NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret);
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goto done;
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}
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}
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ret = nouveau_channel_init(*pchan, arg0, arg1);
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if (ret) {
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NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
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nouveau_channel_del(pchan);
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}
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done:
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cli->base.super = super;
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return ret;
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}
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