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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program see the file copying if not write to the free software foundation 675 mass ave cambridge ma 02139 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 52 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190519154042.342335923@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
298 lines
7.4 KiB
C
298 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* sata_sis.c - Silicon Integrated Systems SATA
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*
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* Maintained by: Uwe Koziolek
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2004 Uwe Koziolek
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/driver-api/libata.rst
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*
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* Hardware documentation available under NDA.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include "sis.h"
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#define DRV_NAME "sata_sis"
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#define DRV_VERSION "1.0"
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enum {
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sis_180 = 0,
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SIS_SCR_PCI_BAR = 5,
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/* PCI configuration registers */
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SIS_GENCTL = 0x54, /* IDE General Control register */
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SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
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SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
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SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
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SIS_PMR = 0x90, /* port mapping register */
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SIS_PMR_COMBINED = 0x30,
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/* random bits */
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SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
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GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
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};
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static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
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static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
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static const struct pci_device_id sis_pci_tbl[] = {
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{ PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
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{ PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
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{ PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
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{ PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
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{ PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */
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{ PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */
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{ } /* terminate list */
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};
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static struct pci_driver sis_pci_driver = {
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.name = DRV_NAME,
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.id_table = sis_pci_tbl,
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.probe = sis_init_one,
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.remove = ata_pci_remove_one,
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#ifdef CONFIG_PM_SLEEP
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.suspend = ata_pci_device_suspend,
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.resume = ata_pci_device_resume,
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#endif
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};
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static struct scsi_host_template sis_sht = {
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ATA_BMDMA_SHT(DRV_NAME),
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};
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static struct ata_port_operations sis_ops = {
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.inherits = &ata_bmdma_port_ops,
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.scr_read = sis_scr_read,
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.scr_write = sis_scr_write,
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};
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static const struct ata_port_info sis_port_info = {
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.flags = ATA_FLAG_SATA,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA6,
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.port_ops = &sis_ops,
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};
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MODULE_AUTHOR("Uwe Koziolek");
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MODULE_DESCRIPTION("low-level driver for Silicon Integrated Systems SATA controller");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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static unsigned int get_scr_cfg_addr(struct ata_link *link, unsigned int sc_reg)
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{
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struct ata_port *ap = link->ap;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
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u8 pmr;
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if (ap->port_no) {
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switch (pdev->device) {
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case 0x0180:
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case 0x0181:
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pci_read_config_byte(pdev, SIS_PMR, &pmr);
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if ((pmr & SIS_PMR_COMBINED) == 0)
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addr += SIS180_SATA1_OFS;
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break;
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case 0x0182:
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case 0x0183:
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case 0x1182:
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addr += SIS182_SATA1_OFS;
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break;
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}
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}
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if (link->pmp)
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addr += 0x10;
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return addr;
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}
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static u32 sis_scr_cfg_read(struct ata_link *link,
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unsigned int sc_reg, u32 *val)
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{
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struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
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unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
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if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
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return -EINVAL;
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pci_read_config_dword(pdev, cfg_addr, val);
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return 0;
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}
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static int sis_scr_cfg_write(struct ata_link *link,
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unsigned int sc_reg, u32 val)
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{
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struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
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unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
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pci_write_config_dword(pdev, cfg_addr, val);
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return 0;
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}
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static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
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{
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struct ata_port *ap = link->ap;
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void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;
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if (sc_reg > SCR_CONTROL)
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return -EINVAL;
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if (ap->flags & SIS_FLAG_CFGSCR)
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return sis_scr_cfg_read(link, sc_reg, val);
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*val = ioread32(base + sc_reg * 4);
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return 0;
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}
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static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
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{
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struct ata_port *ap = link->ap;
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void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;
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if (sc_reg > SCR_CONTROL)
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return -EINVAL;
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if (ap->flags & SIS_FLAG_CFGSCR)
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return sis_scr_cfg_write(link, sc_reg, val);
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iowrite32(val, base + (sc_reg * 4));
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return 0;
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}
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static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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struct ata_port_info pi = sis_port_info;
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const struct ata_port_info *ppi[] = { &pi, &pi };
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struct ata_host *host;
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u32 genctl, val;
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u8 pmr;
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u8 port2_start = 0x20;
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int i, rc;
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ata_print_version_once(&pdev->dev, DRV_VERSION);
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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/* check and see if the SCRs are in IO space or PCI cfg space */
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pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
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if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
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pi.flags |= SIS_FLAG_CFGSCR;
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/* if hardware thinks SCRs are in IO space, but there are
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* no IO resources assigned, change to PCI cfg space.
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*/
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if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
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((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
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(pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
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genctl &= ~GENCTL_IOMAPPED_SCR;
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pci_write_config_dword(pdev, SIS_GENCTL, genctl);
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pi.flags |= SIS_FLAG_CFGSCR;
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}
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pci_read_config_byte(pdev, SIS_PMR, &pmr);
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switch (ent->device) {
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case 0x0180:
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case 0x0181:
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/* The PATA-handling is provided by pata_sis */
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switch (pmr & 0x30) {
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case 0x10:
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ppi[1] = &sis_info133_for_sata;
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break;
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case 0x30:
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ppi[0] = &sis_info133_for_sata;
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break;
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}
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if ((pmr & SIS_PMR_COMBINED) == 0) {
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dev_info(&pdev->dev,
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"Detected SiS 180/181/964 chipset in SATA mode\n");
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port2_start = 64;
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} else {
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dev_info(&pdev->dev,
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"Detected SiS 180/181 chipset in combined mode\n");
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port2_start = 0;
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pi.flags |= ATA_FLAG_SLAVE_POSS;
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}
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break;
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case 0x0182:
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case 0x0183:
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pci_read_config_dword(pdev, 0x6C, &val);
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if (val & (1L << 31)) {
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dev_info(&pdev->dev, "Detected SiS 182/965 chipset\n");
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pi.flags |= ATA_FLAG_SLAVE_POSS;
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} else {
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dev_info(&pdev->dev, "Detected SiS 182/965L chipset\n");
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}
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break;
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case 0x1182:
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dev_info(&pdev->dev,
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"Detected SiS 1182/966/680 SATA controller\n");
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pi.flags |= ATA_FLAG_SLAVE_POSS;
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break;
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case 0x1183:
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dev_info(&pdev->dev,
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"Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
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ppi[0] = &sis_info133_for_sata;
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ppi[1] = &sis_info133_for_sata;
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break;
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}
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rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
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if (rc)
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return rc;
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for (i = 0; i < 2; i++) {
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struct ata_port *ap = host->ports[i];
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if (ap->flags & ATA_FLAG_SATA &&
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ap->flags & ATA_FLAG_SLAVE_POSS) {
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rc = ata_slave_link_init(ap);
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if (rc)
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return rc;
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}
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}
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if (!(pi.flags & SIS_FLAG_CFGSCR)) {
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void __iomem *mmio;
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rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
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if (rc)
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return rc;
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mmio = host->iomap[SIS_SCR_PCI_BAR];
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host->ports[0]->ioaddr.scr_addr = mmio;
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host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
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}
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pci_set_master(pdev);
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pci_intx(pdev, 1);
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return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
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IRQF_SHARED, &sis_sht);
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}
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module_pci_driver(sis_pci_driver);
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