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![Dmitry Osipenko](/assets/img/avatar_default.png)
Add devfreq driver for NVIDIA Tegra20 SoC's. The driver periodically reads out Memory Controller counters and adjusts memory frequency based on the memory clients activity. Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> [Removed MAINTAINERS updates by MyungJoo so that it can be sent elsewhere.] Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
212 lines
5.1 KiB
C
212 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* NVIDIA Tegra20 devfreq driver
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*
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* Copyright (C) 2019 GRATE-DRIVER project
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*/
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#include <linux/clk.h>
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#include <linux/devfreq.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/slab.h>
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#include <soc/tegra/mc.h>
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#include "governor.h"
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#define MC_STAT_CONTROL 0x90
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#define MC_STAT_EMC_CLOCK_LIMIT 0xa0
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#define MC_STAT_EMC_CLOCKS 0xa4
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#define MC_STAT_EMC_CONTROL 0xa8
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#define MC_STAT_EMC_COUNT 0xb8
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#define EMC_GATHER_CLEAR (1 << 8)
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#define EMC_GATHER_ENABLE (3 << 8)
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struct tegra_devfreq {
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struct devfreq *devfreq;
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struct clk *emc_clock;
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void __iomem *regs;
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};
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static int tegra_devfreq_target(struct device *dev, unsigned long *freq,
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u32 flags)
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{
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struct tegra_devfreq *tegra = dev_get_drvdata(dev);
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struct devfreq *devfreq = tegra->devfreq;
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struct dev_pm_opp *opp;
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unsigned long rate;
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int err;
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opp = devfreq_recommended_opp(dev, freq, flags);
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if (IS_ERR(opp))
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return PTR_ERR(opp);
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rate = dev_pm_opp_get_freq(opp);
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dev_pm_opp_put(opp);
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err = clk_set_min_rate(tegra->emc_clock, rate);
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if (err)
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return err;
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err = clk_set_rate(tegra->emc_clock, 0);
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if (err)
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goto restore_min_rate;
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return 0;
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restore_min_rate:
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clk_set_min_rate(tegra->emc_clock, devfreq->previous_freq);
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return err;
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}
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static int tegra_devfreq_get_dev_status(struct device *dev,
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struct devfreq_dev_status *stat)
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{
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struct tegra_devfreq *tegra = dev_get_drvdata(dev);
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/*
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* EMC_COUNT returns number of memory events, that number is lower
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* than the number of clocks. Conversion ratio of 1/8 results in a
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* bit higher bandwidth than actually needed, it is good enough for
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* the time being because drivers don't support requesting minimum
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* needed memory bandwidth yet.
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*
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* TODO: adjust the ratio value once relevant drivers will support
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* memory bandwidth management.
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*/
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stat->busy_time = readl_relaxed(tegra->regs + MC_STAT_EMC_COUNT);
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stat->total_time = readl_relaxed(tegra->regs + MC_STAT_EMC_CLOCKS) / 8;
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stat->current_frequency = clk_get_rate(tegra->emc_clock);
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writel_relaxed(EMC_GATHER_CLEAR, tegra->regs + MC_STAT_CONTROL);
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writel_relaxed(EMC_GATHER_ENABLE, tegra->regs + MC_STAT_CONTROL);
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return 0;
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}
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static struct devfreq_dev_profile tegra_devfreq_profile = {
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.polling_ms = 500,
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.target = tegra_devfreq_target,
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.get_dev_status = tegra_devfreq_get_dev_status,
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};
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static struct tegra_mc *tegra_get_memory_controller(void)
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{
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struct platform_device *pdev;
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struct device_node *np;
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struct tegra_mc *mc;
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np = of_find_compatible_node(NULL, NULL, "nvidia,tegra20-mc-gart");
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if (!np)
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return ERR_PTR(-ENOENT);
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pdev = of_find_device_by_node(np);
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of_node_put(np);
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if (!pdev)
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return ERR_PTR(-ENODEV);
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mc = platform_get_drvdata(pdev);
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if (!mc)
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return ERR_PTR(-EPROBE_DEFER);
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return mc;
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}
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static int tegra_devfreq_probe(struct platform_device *pdev)
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{
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struct tegra_devfreq *tegra;
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struct tegra_mc *mc;
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unsigned long max_rate;
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unsigned long rate;
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int err;
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mc = tegra_get_memory_controller();
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if (IS_ERR(mc)) {
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err = PTR_ERR(mc);
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dev_err(&pdev->dev, "failed to get memory controller: %d\n",
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err);
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return err;
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}
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tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
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if (!tegra)
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return -ENOMEM;
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/* EMC is a system-critical clock that is always enabled */
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tegra->emc_clock = devm_clk_get(&pdev->dev, "emc");
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if (IS_ERR(tegra->emc_clock)) {
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err = PTR_ERR(tegra->emc_clock);
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dev_err(&pdev->dev, "failed to get emc clock: %d\n", err);
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return err;
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}
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tegra->regs = mc->regs;
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max_rate = clk_round_rate(tegra->emc_clock, ULONG_MAX);
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for (rate = 0; rate <= max_rate; rate++) {
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rate = clk_round_rate(tegra->emc_clock, rate);
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err = dev_pm_opp_add(&pdev->dev, rate, 0);
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if (err) {
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dev_err(&pdev->dev, "failed to add opp: %d\n", err);
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goto remove_opps;
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}
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}
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/*
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* Reset statistic gathers state, select global bandwidth for the
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* statistics collection mode and set clocks counter saturation
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* limit to maximum.
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*/
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writel_relaxed(0x00000000, tegra->regs + MC_STAT_CONTROL);
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writel_relaxed(0x00000000, tegra->regs + MC_STAT_EMC_CONTROL);
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writel_relaxed(0xffffffff, tegra->regs + MC_STAT_EMC_CLOCK_LIMIT);
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platform_set_drvdata(pdev, tegra);
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tegra->devfreq = devfreq_add_device(&pdev->dev, &tegra_devfreq_profile,
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DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL);
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if (IS_ERR(tegra->devfreq)) {
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err = PTR_ERR(tegra->devfreq);
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goto remove_opps;
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}
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return 0;
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remove_opps:
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dev_pm_opp_remove_all_dynamic(&pdev->dev);
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return err;
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}
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static int tegra_devfreq_remove(struct platform_device *pdev)
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{
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struct tegra_devfreq *tegra = platform_get_drvdata(pdev);
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devfreq_remove_device(tegra->devfreq);
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dev_pm_opp_remove_all_dynamic(&pdev->dev);
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return 0;
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}
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static struct platform_driver tegra_devfreq_driver = {
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.probe = tegra_devfreq_probe,
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.remove = tegra_devfreq_remove,
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.driver = {
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.name = "tegra20-devfreq",
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},
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};
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module_platform_driver(tegra_devfreq_driver);
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MODULE_ALIAS("platform:tegra20-devfreq");
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MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");
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MODULE_DESCRIPTION("NVIDIA Tegra20 devfreq driver");
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MODULE_LICENSE("GPL v2");
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